1 // Copyright 2017 The ChromiumOS Authors 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 /* 6 * automatically generated by rust-bindgen 7 * From upstream linux msr-index.h at commit: 8 * 806276b7f07a39a1cc3f38bb1ef5c573d4594a38 9 */ 10 11 pub const MSR_EFER: ::std::os::raw::c_uint = 0xc0000080; 12 pub const MSR_STAR: ::std::os::raw::c_uint = 0xc0000081; 13 pub const MSR_LSTAR: ::std::os::raw::c_uint = 0xc0000082; 14 pub const MSR_CSTAR: ::std::os::raw::c_uint = 0xc0000083; 15 pub const MSR_SYSCALL_MASK: ::std::os::raw::c_uint = 0xc0000084; 16 pub const MSR_FS_BASE: ::std::os::raw::c_uint = 0xc0000100; 17 pub const MSR_GS_BASE: ::std::os::raw::c_uint = 0xc0000101; 18 pub const MSR_KERNEL_GS_BASE: ::std::os::raw::c_uint = 0xc0000102; 19 pub const MSR_TSC_AUX: ::std::os::raw::c_uint = 0xc0000103; 20 pub const _EFER_SCE: ::std::os::raw::c_uint = 0x00000000; 21 pub const _EFER_LME: ::std::os::raw::c_uint = 0x00000008; 22 pub const _EFER_LMA: ::std::os::raw::c_uint = 0x0000000a; 23 pub const _EFER_NX: ::std::os::raw::c_uint = 0x0000000b; 24 pub const _EFER_SVME: ::std::os::raw::c_uint = 0x0000000c; 25 pub const _EFER_LMSLE: ::std::os::raw::c_uint = 0x0000000d; 26 pub const _EFER_FFXSR: ::std::os::raw::c_uint = 0x0000000e; 27 pub const EFER_SCE: ::std::os::raw::c_uint = 0x00000001; 28 pub const EFER_LME: ::std::os::raw::c_uint = 0x00000100; 29 pub const EFER_LMA: ::std::os::raw::c_uint = 0x00000400; 30 pub const EFER_NX: ::std::os::raw::c_uint = 0x00000800; 31 pub const EFER_SVME: ::std::os::raw::c_uint = 0x00001000; 32 pub const EFER_LMSLE: ::std::os::raw::c_uint = 0x00002000; 33 pub const EFER_FFXSR: ::std::os::raw::c_uint = 0x00004000; 34 pub const MSR_PPIN_CTL: ::std::os::raw::c_uint = 0x0000004e; 35 pub const MSR_PPIN: ::std::os::raw::c_uint = 0x0000004f; 36 pub const MSR_IA32_PERFCTR0: ::std::os::raw::c_uint = 0x000000c1; 37 pub const MSR_IA32_PERFCTR1: ::std::os::raw::c_uint = 0x000000c2; 38 pub const MSR_FSB_FREQ: ::std::os::raw::c_uint = 0x000000cd; 39 pub const MSR_PLATFORM_INFO: ::std::os::raw::c_uint = 0x000000ce; 40 pub const MSR_PKG_CST_CONFIG_CONTROL: ::std::os::raw::c_uint = 0x000000e2; 41 pub const NHM_C3_AUTO_DEMOTE: ::std::os::raw::c_uint = 0x02000000; 42 pub const NHM_C1_AUTO_DEMOTE: ::std::os::raw::c_uint = 0x04000000; 43 pub const ATM_LNC_C6_AUTO_DEMOTE: ::std::os::raw::c_uint = 0x02000000; 44 pub const SNB_C1_AUTO_UNDEMOTE: ::std::os::raw::c_uint = 0x08000000; 45 pub const SNB_C3_AUTO_UNDEMOTE: ::std::os::raw::c_uint = 0x10000000; 46 pub const MSR_MTRRcap: ::std::os::raw::c_uint = 0x000000fe; 47 pub const MSR_IA32_BBL_CR_CTL: ::std::os::raw::c_uint = 0x00000119; 48 pub const MSR_IA32_BBL_CR_CTL3: ::std::os::raw::c_uint = 0x0000011e; 49 pub const MSR_IA32_SYSENTER_CS: ::std::os::raw::c_uint = 0x00000174; 50 pub const MSR_IA32_SYSENTER_ESP: ::std::os::raw::c_uint = 0x00000175; 51 pub const MSR_IA32_SYSENTER_EIP: ::std::os::raw::c_uint = 0x00000176; 52 pub const MSR_IA32_MCG_CAP: ::std::os::raw::c_uint = 0x00000179; 53 pub const MSR_IA32_MCG_STATUS: ::std::os::raw::c_uint = 0x0000017a; 54 pub const MSR_IA32_MCG_CTL: ::std::os::raw::c_uint = 0x0000017b; 55 pub const MSR_IA32_MCG_EXT_CTL: ::std::os::raw::c_uint = 0x000004d0; 56 pub const MSR_OFFCORE_RSP_0: ::std::os::raw::c_uint = 0x000001a6; 57 pub const MSR_OFFCORE_RSP_1: ::std::os::raw::c_uint = 0x000001a7; 58 pub const MSR_TURBO_RATIO_LIMIT: ::std::os::raw::c_uint = 0x000001ad; 59 pub const MSR_TURBO_RATIO_LIMIT1: ::std::os::raw::c_uint = 0x000001ae; 60 pub const MSR_TURBO_RATIO_LIMIT2: ::std::os::raw::c_uint = 0x000001af; 61 pub const MSR_LBR_SELECT: ::std::os::raw::c_uint = 0x000001c8; 62 pub const MSR_LBR_TOS: ::std::os::raw::c_uint = 0x000001c9; 63 pub const MSR_LBR_NHM_FROM: ::std::os::raw::c_uint = 0x00000680; 64 pub const MSR_LBR_NHM_TO: ::std::os::raw::c_uint = 0x000006c0; 65 pub const MSR_LBR_CORE_FROM: ::std::os::raw::c_uint = 0x00000040; 66 pub const MSR_LBR_CORE_TO: ::std::os::raw::c_uint = 0x00000060; 67 pub const MSR_LBR_INFO_0: ::std::os::raw::c_uint = 0x00000dc0; 68 pub const LBR_INFO_CYCLES: ::std::os::raw::c_uint = 0x0000ffff; 69 pub const MSR_IA32_PEBS_ENABLE: ::std::os::raw::c_uint = 0x000003f1; 70 pub const MSR_IA32_DS_AREA: ::std::os::raw::c_uint = 0x00000600; 71 pub const MSR_IA32_PERF_CAPABILITIES: ::std::os::raw::c_uint = 0x00000345; 72 pub const MSR_PEBS_LD_LAT_THRESHOLD: ::std::os::raw::c_uint = 0x000003f6; 73 pub const MSR_IA32_RTIT_CTL: ::std::os::raw::c_uint = 0x00000570; 74 pub const MSR_IA32_RTIT_STATUS: ::std::os::raw::c_uint = 0x00000571; 75 pub const MSR_IA32_RTIT_ADDR0_A: ::std::os::raw::c_uint = 0x00000580; 76 pub const MSR_IA32_RTIT_ADDR0_B: ::std::os::raw::c_uint = 0x00000581; 77 pub const MSR_IA32_RTIT_ADDR1_A: ::std::os::raw::c_uint = 0x00000582; 78 pub const MSR_IA32_RTIT_ADDR1_B: ::std::os::raw::c_uint = 0x00000583; 79 pub const MSR_IA32_RTIT_ADDR2_A: ::std::os::raw::c_uint = 0x00000584; 80 pub const MSR_IA32_RTIT_ADDR2_B: ::std::os::raw::c_uint = 0x00000585; 81 pub const MSR_IA32_RTIT_ADDR3_A: ::std::os::raw::c_uint = 0x00000586; 82 pub const MSR_IA32_RTIT_ADDR3_B: ::std::os::raw::c_uint = 0x00000587; 83 pub const MSR_IA32_RTIT_CR3_MATCH: ::std::os::raw::c_uint = 0x00000572; 84 pub const MSR_IA32_RTIT_OUTPUT_BASE: ::std::os::raw::c_uint = 0x00000560; 85 pub const MSR_IA32_RTIT_OUTPUT_MASK: ::std::os::raw::c_uint = 0x00000561; 86 pub const MSR_MTRRfix64K_00000: ::std::os::raw::c_uint = 0x00000250; 87 pub const MSR_MTRRfix16K_80000: ::std::os::raw::c_uint = 0x00000258; 88 pub const MSR_MTRRfix16K_A0000: ::std::os::raw::c_uint = 0x00000259; 89 pub const MSR_MTRRfix4K_C0000: ::std::os::raw::c_uint = 0x00000268; 90 pub const MSR_MTRRfix4K_C8000: ::std::os::raw::c_uint = 0x00000269; 91 pub const MSR_MTRRfix4K_D0000: ::std::os::raw::c_uint = 0x0000026a; 92 pub const MSR_MTRRfix4K_D8000: ::std::os::raw::c_uint = 0x0000026b; 93 pub const MSR_MTRRfix4K_E0000: ::std::os::raw::c_uint = 0x0000026c; 94 pub const MSR_MTRRfix4K_E8000: ::std::os::raw::c_uint = 0x0000026d; 95 pub const MSR_MTRRfix4K_F0000: ::std::os::raw::c_uint = 0x0000026e; 96 pub const MSR_MTRRfix4K_F8000: ::std::os::raw::c_uint = 0x0000026f; 97 pub const MSR_MTRRdefType: ::std::os::raw::c_uint = 0x000002ff; 98 pub const MSR_IA32_CR_PAT: ::std::os::raw::c_uint = 0x00000277; 99 pub const MSR_IA32_DEBUGCTLMSR: ::std::os::raw::c_uint = 0x000001d9; 100 pub const MSR_IA32_LASTBRANCHFROMIP: ::std::os::raw::c_uint = 0x000001db; 101 pub const MSR_IA32_LASTBRANCHTOIP: ::std::os::raw::c_uint = 0x000001dc; 102 pub const MSR_IA32_LASTINTFROMIP: ::std::os::raw::c_uint = 0x000001dd; 103 pub const MSR_IA32_LASTINTTOIP: ::std::os::raw::c_uint = 0x000001de; 104 pub const DEBUGCTLMSR_LBR: ::std::os::raw::c_uint = 0x00000001; 105 pub const DEBUGCTLMSR_BTF: ::std::os::raw::c_uint = 0x00000002; 106 pub const DEBUGCTLMSR_TR: ::std::os::raw::c_uint = 0x00000040; 107 pub const DEBUGCTLMSR_BTS: ::std::os::raw::c_uint = 0x00000080; 108 pub const DEBUGCTLMSR_BTINT: ::std::os::raw::c_uint = 0x00000100; 109 pub const DEBUGCTLMSR_BTS_OFF_OS: ::std::os::raw::c_uint = 0x00000200; 110 pub const DEBUGCTLMSR_BTS_OFF_USR: ::std::os::raw::c_uint = 0x00000400; 111 pub const DEBUGCTLMSR_FREEZE_LBRS_ON_PMI: ::std::os::raw::c_uint = 0x00000800; 112 pub const MSR_PEBS_FRONTEND: ::std::os::raw::c_uint = 0x000003f7; 113 pub const MSR_IA32_POWER_CTL: ::std::os::raw::c_uint = 0x000001fc; 114 pub const MSR_IA32_MC0_CTL: ::std::os::raw::c_uint = 0x00000400; 115 pub const MSR_IA32_MC0_STATUS: ::std::os::raw::c_uint = 0x00000401; 116 pub const MSR_IA32_MC0_ADDR: ::std::os::raw::c_uint = 0x00000402; 117 pub const MSR_IA32_MC0_MISC: ::std::os::raw::c_uint = 0x00000403; 118 pub const MSR_PKG_C3_RESIDENCY: ::std::os::raw::c_uint = 0x000003f8; 119 pub const MSR_PKG_C6_RESIDENCY: ::std::os::raw::c_uint = 0x000003f9; 120 pub const MSR_ATOM_PKG_C6_RESIDENCY: ::std::os::raw::c_uint = 0x000003fa; 121 pub const MSR_PKG_C7_RESIDENCY: ::std::os::raw::c_uint = 0x000003fa; 122 pub const MSR_CORE_C3_RESIDENCY: ::std::os::raw::c_uint = 0x000003fc; 123 pub const MSR_CORE_C6_RESIDENCY: ::std::os::raw::c_uint = 0x000003fd; 124 pub const MSR_CORE_C7_RESIDENCY: ::std::os::raw::c_uint = 0x000003fe; 125 pub const MSR_KNL_CORE_C6_RESIDENCY: ::std::os::raw::c_uint = 0x000003ff; 126 pub const MSR_PKG_C2_RESIDENCY: ::std::os::raw::c_uint = 0x0000060d; 127 pub const MSR_PKG_C8_RESIDENCY: ::std::os::raw::c_uint = 0x00000630; 128 pub const MSR_PKG_C9_RESIDENCY: ::std::os::raw::c_uint = 0x00000631; 129 pub const MSR_PKG_C10_RESIDENCY: ::std::os::raw::c_uint = 0x00000632; 130 pub const MSR_PKGC3_IRTL: ::std::os::raw::c_uint = 0x0000060a; 131 pub const MSR_PKGC6_IRTL: ::std::os::raw::c_uint = 0x0000060b; 132 pub const MSR_PKGC7_IRTL: ::std::os::raw::c_uint = 0x0000060c; 133 pub const MSR_PKGC8_IRTL: ::std::os::raw::c_uint = 0x00000633; 134 pub const MSR_PKGC9_IRTL: ::std::os::raw::c_uint = 0x00000634; 135 pub const MSR_PKGC10_IRTL: ::std::os::raw::c_uint = 0x00000635; 136 pub const MSR_RAPL_POWER_UNIT: ::std::os::raw::c_uint = 0x00000606; 137 pub const MSR_PKG_POWER_LIMIT: ::std::os::raw::c_uint = 0x00000610; 138 pub const MSR_PKG_ENERGY_STATUS: ::std::os::raw::c_uint = 0x00000611; 139 pub const MSR_PKG_PERF_STATUS: ::std::os::raw::c_uint = 0x00000613; 140 pub const MSR_PKG_POWER_INFO: ::std::os::raw::c_uint = 0x00000614; 141 pub const MSR_DRAM_POWER_LIMIT: ::std::os::raw::c_uint = 0x00000618; 142 pub const MSR_DRAM_ENERGY_STATUS: ::std::os::raw::c_uint = 0x00000619; 143 pub const MSR_DRAM_PERF_STATUS: ::std::os::raw::c_uint = 0x0000061b; 144 pub const MSR_DRAM_POWER_INFO: ::std::os::raw::c_uint = 0x0000061c; 145 pub const MSR_PP0_POWER_LIMIT: ::std::os::raw::c_uint = 0x00000638; 146 pub const MSR_PP0_ENERGY_STATUS: ::std::os::raw::c_uint = 0x00000639; 147 pub const MSR_PP0_POLICY: ::std::os::raw::c_uint = 0x0000063a; 148 pub const MSR_PP0_PERF_STATUS: ::std::os::raw::c_uint = 0x0000063b; 149 pub const MSR_PP1_POWER_LIMIT: ::std::os::raw::c_uint = 0x00000640; 150 pub const MSR_PP1_ENERGY_STATUS: ::std::os::raw::c_uint = 0x00000641; 151 pub const MSR_PP1_POLICY: ::std::os::raw::c_uint = 0x00000642; 152 pub const MSR_CONFIG_TDP_NOMINAL: ::std::os::raw::c_uint = 0x00000648; 153 pub const MSR_CONFIG_TDP_LEVEL_1: ::std::os::raw::c_uint = 0x00000649; 154 pub const MSR_CONFIG_TDP_LEVEL_2: ::std::os::raw::c_uint = 0x0000064a; 155 pub const MSR_CONFIG_TDP_CONTROL: ::std::os::raw::c_uint = 0x0000064b; 156 pub const MSR_TURBO_ACTIVATION_RATIO: ::std::os::raw::c_uint = 0x0000064c; 157 pub const MSR_PLATFORM_ENERGY_STATUS: ::std::os::raw::c_uint = 0x0000064d; 158 pub const MSR_PKG_WEIGHTED_CORE_C0_RES: ::std::os::raw::c_uint = 0x00000658; 159 pub const MSR_PKG_ANY_CORE_C0_RES: ::std::os::raw::c_uint = 0x00000659; 160 pub const MSR_PKG_ANY_GFXE_C0_RES: ::std::os::raw::c_uint = 0x0000065a; 161 pub const MSR_PKG_BOTH_CORE_GFXE_C0_RES: ::std::os::raw::c_uint = 0x0000065b; 162 pub const MSR_CORE_C1_RES: ::std::os::raw::c_uint = 0x00000660; 163 pub const MSR_MODULE_C6_RES_MS: ::std::os::raw::c_uint = 0x00000664; 164 pub const MSR_CC6_DEMOTION_POLICY_CONFIG: ::std::os::raw::c_uint = 0x00000668; 165 pub const MSR_MC6_DEMOTION_POLICY_CONFIG: ::std::os::raw::c_uint = 0x00000669; 166 pub const MSR_ATOM_CORE_RATIOS: ::std::os::raw::c_uint = 0x0000066a; 167 pub const MSR_ATOM_CORE_VIDS: ::std::os::raw::c_uint = 0x0000066b; 168 pub const MSR_ATOM_CORE_TURBO_RATIOS: ::std::os::raw::c_uint = 0x0000066c; 169 pub const MSR_ATOM_CORE_TURBO_VIDS: ::std::os::raw::c_uint = 0x0000066d; 170 pub const MSR_CORE_PERF_LIMIT_REASONS: ::std::os::raw::c_uint = 0x00000690; 171 pub const MSR_GFX_PERF_LIMIT_REASONS: ::std::os::raw::c_uint = 0x000006b0; 172 pub const MSR_RING_PERF_LIMIT_REASONS: ::std::os::raw::c_uint = 0x000006b1; 173 pub const MSR_PPERF: ::std::os::raw::c_uint = 0x0000064e; 174 pub const MSR_PERF_LIMIT_REASONS: ::std::os::raw::c_uint = 0x0000064f; 175 pub const MSR_PM_ENABLE: ::std::os::raw::c_uint = 0x00000770; 176 pub const MSR_HWP_CAPABILITIES: ::std::os::raw::c_uint = 0x00000771; 177 pub const MSR_HWP_REQUEST_PKG: ::std::os::raw::c_uint = 0x00000772; 178 pub const MSR_HWP_INTERRUPT: ::std::os::raw::c_uint = 0x00000773; 179 pub const MSR_HWP_REQUEST: ::std::os::raw::c_uint = 0x00000774; 180 pub const MSR_HWP_STATUS: ::std::os::raw::c_uint = 0x00000777; 181 pub const HWP_BASE_BIT: ::std::os::raw::c_uint = 0x00000080; 182 pub const HWP_NOTIFICATIONS_BIT: ::std::os::raw::c_uint = 0x00000100; 183 pub const HWP_ACTIVITY_WINDOW_BIT: ::std::os::raw::c_uint = 0x00000200; 184 pub const HWP_ENERGY_PERF_PREFERENCE_BIT: ::std::os::raw::c_uint = 0x00000400; 185 pub const HWP_PACKAGE_LEVEL_REQUEST_BIT: ::std::os::raw::c_uint = 0x00000800; 186 pub const MSR_AMD64_MC0_MASK: ::std::os::raw::c_uint = 0xc0010044; 187 pub const MSR_IA32_MC0_CTL2: ::std::os::raw::c_uint = 0x00000280; 188 pub const MSR_P6_PERFCTR0: ::std::os::raw::c_uint = 0x000000c1; 189 pub const MSR_P6_PERFCTR1: ::std::os::raw::c_uint = 0x000000c2; 190 pub const MSR_P6_EVNTSEL0: ::std::os::raw::c_uint = 0x00000186; 191 pub const MSR_P6_EVNTSEL1: ::std::os::raw::c_uint = 0x00000187; 192 pub const MSR_KNC_PERFCTR0: ::std::os::raw::c_uint = 0x00000020; 193 pub const MSR_KNC_PERFCTR1: ::std::os::raw::c_uint = 0x00000021; 194 pub const MSR_KNC_EVNTSEL0: ::std::os::raw::c_uint = 0x00000028; 195 pub const MSR_KNC_EVNTSEL1: ::std::os::raw::c_uint = 0x00000029; 196 pub const MSR_IA32_PMC0: ::std::os::raw::c_uint = 0x000004c1; 197 pub const MSR_AMD64_PATCH_LEVEL: ::std::os::raw::c_uint = 0x0000008b; 198 pub const MSR_AMD64_TSC_RATIO: ::std::os::raw::c_uint = 0xc0000104; 199 pub const MSR_AMD64_NB_CFG: ::std::os::raw::c_uint = 0xc001001f; 200 pub const MSR_AMD64_PATCH_LOADER: ::std::os::raw::c_uint = 0xc0010020; 201 pub const MSR_AMD64_OSVW_ID_LENGTH: ::std::os::raw::c_uint = 0xc0010140; 202 pub const MSR_AMD64_OSVW_STATUS: ::std::os::raw::c_uint = 0xc0010141; 203 pub const MSR_AMD64_LS_CFG: ::std::os::raw::c_uint = 0xc0011020; 204 pub const MSR_AMD64_DC_CFG: ::std::os::raw::c_uint = 0xc0011022; 205 pub const MSR_AMD64_BU_CFG2: ::std::os::raw::c_uint = 0xc001102a; 206 pub const MSR_AMD64_IBSFETCHCTL: ::std::os::raw::c_uint = 0xc0011030; 207 pub const MSR_AMD64_IBSFETCHLINAD: ::std::os::raw::c_uint = 0xc0011031; 208 pub const MSR_AMD64_IBSFETCHPHYSAD: ::std::os::raw::c_uint = 0xc0011032; 209 pub const MSR_AMD64_IBSFETCH_REG_COUNT: ::std::os::raw::c_uint = 0x00000003; 210 pub const MSR_AMD64_IBSFETCH_REG_MASK: ::std::os::raw::c_uint = 0x00000007; 211 pub const MSR_AMD64_IBSOPCTL: ::std::os::raw::c_uint = 0xc0011033; 212 pub const MSR_AMD64_IBSOPRIP: ::std::os::raw::c_uint = 0xc0011034; 213 pub const MSR_AMD64_IBSOPDATA: ::std::os::raw::c_uint = 0xc0011035; 214 pub const MSR_AMD64_IBSOPDATA2: ::std::os::raw::c_uint = 0xc0011036; 215 pub const MSR_AMD64_IBSOPDATA3: ::std::os::raw::c_uint = 0xc0011037; 216 pub const MSR_AMD64_IBSDCLINAD: ::std::os::raw::c_uint = 0xc0011038; 217 pub const MSR_AMD64_IBSDCPHYSAD: ::std::os::raw::c_uint = 0xc0011039; 218 pub const MSR_AMD64_IBSOP_REG_COUNT: ::std::os::raw::c_uint = 0x00000007; 219 pub const MSR_AMD64_IBSOP_REG_MASK: ::std::os::raw::c_uint = 0x0000007f; 220 pub const MSR_AMD64_IBSCTL: ::std::os::raw::c_uint = 0xc001103a; 221 pub const MSR_AMD64_IBSBRTARGET: ::std::os::raw::c_uint = 0xc001103b; 222 pub const MSR_AMD64_IBSOPDATA4: ::std::os::raw::c_uint = 0xc001103d; 223 pub const MSR_AMD64_IBS_REG_COUNT_MAX: ::std::os::raw::c_uint = 0x00000008; 224 pub const MSR_F17H_IRPERF: ::std::os::raw::c_uint = 0xc00000e9; 225 pub const MSR_F16H_L2I_PERF_CTL: ::std::os::raw::c_uint = 0xc0010230; 226 pub const MSR_F16H_L2I_PERF_CTR: ::std::os::raw::c_uint = 0xc0010231; 227 pub const MSR_F16H_DR1_ADDR_MASK: ::std::os::raw::c_uint = 0xc0011019; 228 pub const MSR_F16H_DR2_ADDR_MASK: ::std::os::raw::c_uint = 0xc001101a; 229 pub const MSR_F16H_DR3_ADDR_MASK: ::std::os::raw::c_uint = 0xc001101b; 230 pub const MSR_F16H_DR0_ADDR_MASK: ::std::os::raw::c_uint = 0xc0011027; 231 pub const MSR_F15H_PERF_CTL: ::std::os::raw::c_uint = 0xc0010200; 232 pub const MSR_F15H_PERF_CTR: ::std::os::raw::c_uint = 0xc0010201; 233 pub const MSR_F15H_NB_PERF_CTL: ::std::os::raw::c_uint = 0xc0010240; 234 pub const MSR_F15H_NB_PERF_CTR: ::std::os::raw::c_uint = 0xc0010241; 235 pub const MSR_F15H_PTSC: ::std::os::raw::c_uint = 0xc0010280; 236 pub const MSR_F15H_IC_CFG: ::std::os::raw::c_uint = 0xc0011021; 237 pub const MSR_FAM10H_MMIO_CONF_BASE: ::std::os::raw::c_uint = 0xc0010058; 238 pub const FAM10H_MMIO_CONF_ENABLE: ::std::os::raw::c_uint = 0x00000001; 239 pub const FAM10H_MMIO_CONF_BUSRANGE_MASK: ::std::os::raw::c_uint = 0x0000000f; 240 pub const FAM10H_MMIO_CONF_BUSRANGE_SHIFT: ::std::os::raw::c_uint = 0x00000002; 241 pub const FAM10H_MMIO_CONF_BASE_MASK: ::std::os::raw::c_uint = 0x0fffffff; 242 pub const FAM10H_MMIO_CONF_BASE_SHIFT: ::std::os::raw::c_uint = 0x00000014; 243 pub const MSR_FAM10H_NODE_ID: ::std::os::raw::c_uint = 0xc001100c; 244 pub const MSR_K8_TOP_MEM1: ::std::os::raw::c_uint = 0xc001001a; 245 pub const MSR_K8_TOP_MEM2: ::std::os::raw::c_uint = 0xc001001d; 246 pub const MSR_K8_SYSCFG: ::std::os::raw::c_uint = 0xc0010010; 247 pub const MSR_K8_INT_PENDING_MSG: ::std::os::raw::c_uint = 0xc0010055; 248 pub const K8_INTP_C1E_ACTIVE_MASK: ::std::os::raw::c_uint = 0x18000000; 249 pub const MSR_K8_TSEG_ADDR: ::std::os::raw::c_uint = 0xc0010112; 250 pub const MSR_K8_TSEG_MASK: ::std::os::raw::c_uint = 0xc0010113; 251 pub const K8_MTRRFIXRANGE_DRAM_ENABLE: ::std::os::raw::c_uint = 0x00040000; 252 pub const K8_MTRRFIXRANGE_DRAM_MODIFY: ::std::os::raw::c_uint = 0x00080000; 253 pub const K8_MTRR_RDMEM_WRMEM_MASK: ::std::os::raw::c_uint = 0x18181818; 254 pub const MSR_K7_EVNTSEL0: ::std::os::raw::c_uint = 0xc0010000; 255 pub const MSR_K7_PERFCTR0: ::std::os::raw::c_uint = 0xc0010004; 256 pub const MSR_K7_EVNTSEL1: ::std::os::raw::c_uint = 0xc0010001; 257 pub const MSR_K7_PERFCTR1: ::std::os::raw::c_uint = 0xc0010005; 258 pub const MSR_K7_EVNTSEL2: ::std::os::raw::c_uint = 0xc0010002; 259 pub const MSR_K7_PERFCTR2: ::std::os::raw::c_uint = 0xc0010006; 260 pub const MSR_K7_EVNTSEL3: ::std::os::raw::c_uint = 0xc0010003; 261 pub const MSR_K7_PERFCTR3: ::std::os::raw::c_uint = 0xc0010007; 262 pub const MSR_K7_CLK_CTL: ::std::os::raw::c_uint = 0xc001001b; 263 pub const MSR_K7_HWCR: ::std::os::raw::c_uint = 0xc0010015; 264 pub const MSR_K7_FID_VID_CTL: ::std::os::raw::c_uint = 0xc0010041; 265 pub const MSR_K7_FID_VID_STATUS: ::std::os::raw::c_uint = 0xc0010042; 266 pub const MSR_K6_WHCR: ::std::os::raw::c_uint = 0xc0000082; 267 pub const MSR_K6_UWCCR: ::std::os::raw::c_uint = 0xc0000085; 268 pub const MSR_K6_EPMR: ::std::os::raw::c_uint = 0xc0000086; 269 pub const MSR_K6_PSOR: ::std::os::raw::c_uint = 0xc0000087; 270 pub const MSR_K6_PFIR: ::std::os::raw::c_uint = 0xc0000088; 271 pub const MSR_IDT_FCR1: ::std::os::raw::c_uint = 0x00000107; 272 pub const MSR_IDT_FCR2: ::std::os::raw::c_uint = 0x00000108; 273 pub const MSR_IDT_FCR3: ::std::os::raw::c_uint = 0x00000109; 274 pub const MSR_IDT_FCR4: ::std::os::raw::c_uint = 0x0000010a; 275 pub const MSR_IDT_MCR0: ::std::os::raw::c_uint = 0x00000110; 276 pub const MSR_IDT_MCR1: ::std::os::raw::c_uint = 0x00000111; 277 pub const MSR_IDT_MCR2: ::std::os::raw::c_uint = 0x00000112; 278 pub const MSR_IDT_MCR3: ::std::os::raw::c_uint = 0x00000113; 279 pub const MSR_IDT_MCR4: ::std::os::raw::c_uint = 0x00000114; 280 pub const MSR_IDT_MCR5: ::std::os::raw::c_uint = 0x00000115; 281 pub const MSR_IDT_MCR6: ::std::os::raw::c_uint = 0x00000116; 282 pub const MSR_IDT_MCR7: ::std::os::raw::c_uint = 0x00000117; 283 pub const MSR_IDT_MCR_CTRL: ::std::os::raw::c_uint = 0x00000120; 284 pub const MSR_VIA_FCR: ::std::os::raw::c_uint = 0x00001107; 285 pub const MSR_VIA_LONGHAUL: ::std::os::raw::c_uint = 0x0000110a; 286 pub const MSR_VIA_RNG: ::std::os::raw::c_uint = 0x0000110b; 287 pub const MSR_VIA_BCR2: ::std::os::raw::c_uint = 0x00001147; 288 pub const MSR_TMTA_LONGRUN_CTRL: ::std::os::raw::c_uint = 0x80868010; 289 pub const MSR_TMTA_LONGRUN_FLAGS: ::std::os::raw::c_uint = 0x80868011; 290 pub const MSR_TMTA_LRTI_READOUT: ::std::os::raw::c_uint = 0x80868018; 291 pub const MSR_TMTA_LRTI_VOLT_MHZ: ::std::os::raw::c_uint = 0x8086801a; 292 pub const MSR_IA32_P5_MC_ADDR: ::std::os::raw::c_uint = 0x00000000; 293 pub const MSR_IA32_P5_MC_TYPE: ::std::os::raw::c_uint = 0x00000001; 294 pub const MSR_IA32_TSC: ::std::os::raw::c_uint = 0x00000010; 295 pub const MSR_IA32_PLATFORM_ID: ::std::os::raw::c_uint = 0x00000017; 296 pub const MSR_IA32_EBL_CR_POWERON: ::std::os::raw::c_uint = 0x0000002a; 297 pub const MSR_EBC_FREQUENCY_ID: ::std::os::raw::c_uint = 0x0000002c; 298 pub const MSR_SMI_COUNT: ::std::os::raw::c_uint = 0x00000034; 299 pub const MSR_IA32_FEATURE_CONTROL: ::std::os::raw::c_uint = 0x0000003a; 300 pub const MSR_IA32_TSC_ADJUST: ::std::os::raw::c_uint = 0x0000003b; 301 pub const MSR_IA32_BNDCFGS: ::std::os::raw::c_uint = 0x00000d90; 302 pub const MSR_IA32_XSS: ::std::os::raw::c_uint = 0x00000da0; 303 pub const FEATURE_CONTROL_LOCKED: ::std::os::raw::c_uint = 0x00000001; 304 pub const FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX: ::std::os::raw::c_uint = 0x00000002; 305 pub const FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX: ::std::os::raw::c_uint = 0x00000004; 306 pub const FEATURE_CONTROL_LMCE: ::std::os::raw::c_uint = 0x00100000; 307 pub const MSR_IA32_APICBASE: ::std::os::raw::c_uint = 0x0000001b; 308 pub const MSR_IA32_APICBASE_BSP: ::std::os::raw::c_uint = 0x00000100; 309 pub const MSR_IA32_APICBASE_ENABLE: ::std::os::raw::c_uint = 0x00000800; 310 pub const MSR_IA32_APICBASE_BASE: ::std::os::raw::c_uint = 0xfffff000; 311 pub const MSR_IA32_TSCDEADLINE: ::std::os::raw::c_uint = 0x000006e0; 312 pub const MSR_IA32_UCODE_WRITE: ::std::os::raw::c_uint = 0x00000079; 313 pub const MSR_IA32_UCODE_REV: ::std::os::raw::c_uint = 0x0000008b; 314 pub const MSR_IA32_SMM_MONITOR_CTL: ::std::os::raw::c_uint = 0x0000009b; 315 pub const MSR_IA32_SMBASE: ::std::os::raw::c_uint = 0x0000009e; 316 pub const MSR_IA32_PERF_STATUS: ::std::os::raw::c_uint = 0x00000198; 317 pub const MSR_IA32_PERF_CTL: ::std::os::raw::c_uint = 0x00000199; 318 pub const INTEL_PERF_CTL_MASK: ::std::os::raw::c_uint = 0x0000ffff; 319 pub const MSR_AMD_PSTATE_DEF_BASE: ::std::os::raw::c_uint = 0xc0010064; 320 pub const MSR_AMD_PERF_STATUS: ::std::os::raw::c_uint = 0xc0010063; 321 pub const MSR_AMD_PERF_CTL: ::std::os::raw::c_uint = 0xc0010062; 322 pub const MSR_IA32_MPERF: ::std::os::raw::c_uint = 0x000000e7; 323 pub const MSR_IA32_APERF: ::std::os::raw::c_uint = 0x000000e8; 324 pub const MSR_IA32_THERM_CONTROL: ::std::os::raw::c_uint = 0x0000019a; 325 pub const MSR_IA32_THERM_INTERRUPT: ::std::os::raw::c_uint = 0x0000019b; 326 pub const THERM_INT_HIGH_ENABLE: ::std::os::raw::c_uint = 0x00000001; 327 pub const THERM_INT_LOW_ENABLE: ::std::os::raw::c_uint = 0x00000002; 328 pub const THERM_INT_PLN_ENABLE: ::std::os::raw::c_uint = 0x01000000; 329 pub const MSR_IA32_THERM_STATUS: ::std::os::raw::c_uint = 0x0000019c; 330 pub const THERM_STATUS_PROCHOT: ::std::os::raw::c_uint = 0x00000001; 331 pub const THERM_STATUS_POWER_LIMIT: ::std::os::raw::c_uint = 0x00000400; 332 pub const MSR_THERM2_CTL: ::std::os::raw::c_uint = 0x0000019d; 333 pub const MSR_THERM2_CTL_TM_SELECT: ::std::os::raw::c_uint = 0x00010000; 334 pub const MSR_IA32_MISC_ENABLE: ::std::os::raw::c_uint = 0x000001a0; 335 pub const MSR_IA32_TEMPERATURE_TARGET: ::std::os::raw::c_uint = 0x000001a2; 336 pub const MSR_MISC_FEATURE_CONTROL: ::std::os::raw::c_uint = 0x000001a4; 337 pub const MSR_MISC_PWR_MGMT: ::std::os::raw::c_uint = 0x000001aa; 338 pub const MSR_IA32_ENERGY_PERF_BIAS: ::std::os::raw::c_uint = 0x000001b0; 339 pub const ENERGY_PERF_BIAS_PERFORMANCE: ::std::os::raw::c_uint = 0x00000000; 340 pub const ENERGY_PERF_BIAS_NORMAL: ::std::os::raw::c_uint = 0x00000006; 341 pub const ENERGY_PERF_BIAS_POWERSAVE: ::std::os::raw::c_uint = 0x0000000f; 342 pub const MSR_IA32_PACKAGE_THERM_STATUS: ::std::os::raw::c_uint = 0x000001b1; 343 pub const PACKAGE_THERM_STATUS_PROCHOT: ::std::os::raw::c_uint = 0x00000001; 344 pub const PACKAGE_THERM_STATUS_POWER_LIMIT: ::std::os::raw::c_uint = 0x00000400; 345 pub const MSR_IA32_PACKAGE_THERM_INTERRUPT: ::std::os::raw::c_uint = 0x000001b2; 346 pub const PACKAGE_THERM_INT_HIGH_ENABLE: ::std::os::raw::c_uint = 0x00000001; 347 pub const PACKAGE_THERM_INT_LOW_ENABLE: ::std::os::raw::c_uint = 0x00000002; 348 pub const PACKAGE_THERM_INT_PLN_ENABLE: ::std::os::raw::c_uint = 0x01000000; 349 pub const THERM_INT_THRESHOLD0_ENABLE: ::std::os::raw::c_uint = 0x00008000; 350 pub const THERM_SHIFT_THRESHOLD0: ::std::os::raw::c_uint = 0x00000008; 351 pub const THERM_MASK_THRESHOLD0: ::std::os::raw::c_uint = 0x00007f00; 352 pub const THERM_INT_THRESHOLD1_ENABLE: ::std::os::raw::c_uint = 0x00800000; 353 pub const THERM_SHIFT_THRESHOLD1: ::std::os::raw::c_uint = 0x00000010; 354 pub const THERM_MASK_THRESHOLD1: ::std::os::raw::c_uint = 0x007f0000; 355 pub const THERM_STATUS_THRESHOLD0: ::std::os::raw::c_uint = 0x00000040; 356 pub const THERM_LOG_THRESHOLD0: ::std::os::raw::c_uint = 0x00000080; 357 pub const THERM_STATUS_THRESHOLD1: ::std::os::raw::c_uint = 0x00000100; 358 pub const THERM_LOG_THRESHOLD1: ::std::os::raw::c_uint = 0x00000200; 359 pub const MSR_IA32_MISC_ENABLE_FAST_STRING_BIT: ::std::os::raw::c_uint = 0x00000000; 360 pub const MSR_IA32_MISC_ENABLE_FAST_STRING: ::std::os::raw::c_uint = 0x00000001; 361 pub const MSR_IA32_MISC_ENABLE_TCC_BIT: ::std::os::raw::c_uint = 0x00000001; 362 pub const MSR_IA32_MISC_ENABLE_TCC: ::std::os::raw::c_uint = 0x00000002; 363 pub const MSR_IA32_MISC_ENABLE_EMON_BIT: ::std::os::raw::c_uint = 0x00000007; 364 pub const MSR_IA32_MISC_ENABLE_EMON: ::std::os::raw::c_uint = 0x00000080; 365 pub const MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT: ::std::os::raw::c_uint = 0x0000000b; 366 pub const MSR_IA32_MISC_ENABLE_BTS_UNAVAIL: ::std::os::raw::c_uint = 0x00000800; 367 pub const MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT: ::std::os::raw::c_uint = 0x0000000c; 368 pub const MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL: ::std::os::raw::c_uint = 0x00001000; 369 pub const MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT: ::std::os::raw::c_uint = 0x00000010; 370 pub const MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP: ::std::os::raw::c_uint = 0x00010000; 371 pub const MSR_IA32_MISC_ENABLE_MWAIT_BIT: ::std::os::raw::c_uint = 0x00000012; 372 pub const MSR_IA32_MISC_ENABLE_MWAIT: ::std::os::raw::c_uint = 0x00040000; 373 pub const MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT: ::std::os::raw::c_uint = 0x00000016; 374 pub const MSR_IA32_MISC_ENABLE_LIMIT_CPUID: ::std::os::raw::c_uint = 0x00400000; 375 pub const MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT: ::std::os::raw::c_uint = 0x00000017; 376 pub const MSR_IA32_MISC_ENABLE_XTPR_DISABLE: ::std::os::raw::c_uint = 0x00800000; 377 pub const MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT: ::std::os::raw::c_uint = 0x00000022; 378 pub const MSR_IA32_MISC_ENABLE_XD_DISABLE: ::std::os::raw::c_ulonglong = 0x400000000; 379 pub const MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT: ::std::os::raw::c_uint = 0x00000002; 380 pub const MSR_IA32_MISC_ENABLE_X87_COMPAT: ::std::os::raw::c_uint = 0x00000004; 381 pub const MSR_IA32_MISC_ENABLE_TM1_BIT: ::std::os::raw::c_uint = 0x00000003; 382 pub const MSR_IA32_MISC_ENABLE_TM1: ::std::os::raw::c_uint = 0x00000008; 383 pub const MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT: ::std::os::raw::c_uint = 0x00000004; 384 pub const MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE: ::std::os::raw::c_uint = 0x00000010; 385 pub const MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT: ::std::os::raw::c_uint = 0x00000006; 386 pub const MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE: ::std::os::raw::c_uint = 0x00000040; 387 pub const MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT: ::std::os::raw::c_uint = 0x00000008; 388 pub const MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK: ::std::os::raw::c_uint = 0x00000100; 389 pub const MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT: ::std::os::raw::c_uint = 0x00000009; 390 pub const MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE: ::std::os::raw::c_uint = 0x00000200; 391 pub const MSR_IA32_MISC_ENABLE_FERR_BIT: ::std::os::raw::c_uint = 0x0000000a; 392 pub const MSR_IA32_MISC_ENABLE_FERR: ::std::os::raw::c_uint = 0x00000400; 393 pub const MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT: ::std::os::raw::c_uint = 0x0000000a; 394 pub const MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX: ::std::os::raw::c_uint = 0x00000400; 395 pub const MSR_IA32_MISC_ENABLE_TM2_BIT: ::std::os::raw::c_uint = 0x0000000d; 396 pub const MSR_IA32_MISC_ENABLE_TM2: ::std::os::raw::c_uint = 0x00002000; 397 pub const MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT: ::std::os::raw::c_uint = 0x00000013; 398 pub const MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE: ::std::os::raw::c_uint = 0x00080000; 399 pub const MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT: ::std::os::raw::c_uint = 0x00000014; 400 pub const MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK: ::std::os::raw::c_uint = 0x00100000; 401 pub const MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT: ::std::os::raw::c_uint = 0x00000018; 402 pub const MSR_IA32_MISC_ENABLE_L1D_CONTEXT: ::std::os::raw::c_uint = 0x01000000; 403 pub const MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT: ::std::os::raw::c_uint = 0x00000025; 404 pub const MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE: ::std::os::raw::c_ulonglong = 0x2000000000; 405 pub const MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT: ::std::os::raw::c_uint = 0x00000026; 406 pub const MSR_IA32_MISC_ENABLE_TURBO_DISABLE: ::std::os::raw::c_ulonglong = 0x4000000000; 407 pub const MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT: ::std::os::raw::c_uint = 0x00000027; 408 pub const MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE: ::std::os::raw::c_ulonglong = 0x8000000000; 409 pub const MSR_MISC_FEATURE_ENABLES: ::std::os::raw::c_uint = 0x00000140; 410 pub const MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT: ::std::os::raw::c_uint = 0x00000001; 411 pub const MSR_IA32_TSC_DEADLINE: ::std::os::raw::c_uint = 0x000006e0; 412 pub const MSR_IA32_MCG_EAX: ::std::os::raw::c_uint = 0x00000180; 413 pub const MSR_IA32_MCG_EBX: ::std::os::raw::c_uint = 0x00000181; 414 pub const MSR_IA32_MCG_ECX: ::std::os::raw::c_uint = 0x00000182; 415 pub const MSR_IA32_MCG_EDX: ::std::os::raw::c_uint = 0x00000183; 416 pub const MSR_IA32_MCG_ESI: ::std::os::raw::c_uint = 0x00000184; 417 pub const MSR_IA32_MCG_EDI: ::std::os::raw::c_uint = 0x00000185; 418 pub const MSR_IA32_MCG_EBP: ::std::os::raw::c_uint = 0x00000186; 419 pub const MSR_IA32_MCG_ESP: ::std::os::raw::c_uint = 0x00000187; 420 pub const MSR_IA32_MCG_EFLAGS: ::std::os::raw::c_uint = 0x00000188; 421 pub const MSR_IA32_MCG_EIP: ::std::os::raw::c_uint = 0x00000189; 422 pub const MSR_IA32_MCG_RESERVED: ::std::os::raw::c_uint = 0x0000018a; 423 pub const MSR_P4_BPU_PERFCTR0: ::std::os::raw::c_uint = 0x00000300; 424 pub const MSR_P4_BPU_PERFCTR1: ::std::os::raw::c_uint = 0x00000301; 425 pub const MSR_P4_BPU_PERFCTR2: ::std::os::raw::c_uint = 0x00000302; 426 pub const MSR_P4_BPU_PERFCTR3: ::std::os::raw::c_uint = 0x00000303; 427 pub const MSR_P4_MS_PERFCTR0: ::std::os::raw::c_uint = 0x00000304; 428 pub const MSR_P4_MS_PERFCTR1: ::std::os::raw::c_uint = 0x00000305; 429 pub const MSR_P4_MS_PERFCTR2: ::std::os::raw::c_uint = 0x00000306; 430 pub const MSR_P4_MS_PERFCTR3: ::std::os::raw::c_uint = 0x00000307; 431 pub const MSR_P4_FLAME_PERFCTR0: ::std::os::raw::c_uint = 0x00000308; 432 pub const MSR_P4_FLAME_PERFCTR1: ::std::os::raw::c_uint = 0x00000309; 433 pub const MSR_P4_FLAME_PERFCTR2: ::std::os::raw::c_uint = 0x0000030a; 434 pub const MSR_P4_FLAME_PERFCTR3: ::std::os::raw::c_uint = 0x0000030b; 435 pub const MSR_P4_IQ_PERFCTR0: ::std::os::raw::c_uint = 0x0000030c; 436 pub const MSR_P4_IQ_PERFCTR1: ::std::os::raw::c_uint = 0x0000030d; 437 pub const MSR_P4_IQ_PERFCTR2: ::std::os::raw::c_uint = 0x0000030e; 438 pub const MSR_P4_IQ_PERFCTR3: ::std::os::raw::c_uint = 0x0000030f; 439 pub const MSR_P4_IQ_PERFCTR4: ::std::os::raw::c_uint = 0x00000310; 440 pub const MSR_P4_IQ_PERFCTR5: ::std::os::raw::c_uint = 0x00000311; 441 pub const MSR_P4_BPU_CCCR0: ::std::os::raw::c_uint = 0x00000360; 442 pub const MSR_P4_BPU_CCCR1: ::std::os::raw::c_uint = 0x00000361; 443 pub const MSR_P4_BPU_CCCR2: ::std::os::raw::c_uint = 0x00000362; 444 pub const MSR_P4_BPU_CCCR3: ::std::os::raw::c_uint = 0x00000363; 445 pub const MSR_P4_MS_CCCR0: ::std::os::raw::c_uint = 0x00000364; 446 pub const MSR_P4_MS_CCCR1: ::std::os::raw::c_uint = 0x00000365; 447 pub const MSR_P4_MS_CCCR2: ::std::os::raw::c_uint = 0x00000366; 448 pub const MSR_P4_MS_CCCR3: ::std::os::raw::c_uint = 0x00000367; 449 pub const MSR_P4_FLAME_CCCR0: ::std::os::raw::c_uint = 0x00000368; 450 pub const MSR_P4_FLAME_CCCR1: ::std::os::raw::c_uint = 0x00000369; 451 pub const MSR_P4_FLAME_CCCR2: ::std::os::raw::c_uint = 0x0000036a; 452 pub const MSR_P4_FLAME_CCCR3: ::std::os::raw::c_uint = 0x0000036b; 453 pub const MSR_P4_IQ_CCCR0: ::std::os::raw::c_uint = 0x0000036c; 454 pub const MSR_P4_IQ_CCCR1: ::std::os::raw::c_uint = 0x0000036d; 455 pub const MSR_P4_IQ_CCCR2: ::std::os::raw::c_uint = 0x0000036e; 456 pub const MSR_P4_IQ_CCCR3: ::std::os::raw::c_uint = 0x0000036f; 457 pub const MSR_P4_IQ_CCCR4: ::std::os::raw::c_uint = 0x00000370; 458 pub const MSR_P4_IQ_CCCR5: ::std::os::raw::c_uint = 0x00000371; 459 pub const MSR_P4_ALF_ESCR0: ::std::os::raw::c_uint = 0x000003ca; 460 pub const MSR_P4_ALF_ESCR1: ::std::os::raw::c_uint = 0x000003cb; 461 pub const MSR_P4_BPU_ESCR0: ::std::os::raw::c_uint = 0x000003b2; 462 pub const MSR_P4_BPU_ESCR1: ::std::os::raw::c_uint = 0x000003b3; 463 pub const MSR_P4_BSU_ESCR0: ::std::os::raw::c_uint = 0x000003a0; 464 pub const MSR_P4_BSU_ESCR1: ::std::os::raw::c_uint = 0x000003a1; 465 pub const MSR_P4_CRU_ESCR0: ::std::os::raw::c_uint = 0x000003b8; 466 pub const MSR_P4_CRU_ESCR1: ::std::os::raw::c_uint = 0x000003b9; 467 pub const MSR_P4_CRU_ESCR2: ::std::os::raw::c_uint = 0x000003cc; 468 pub const MSR_P4_CRU_ESCR3: ::std::os::raw::c_uint = 0x000003cd; 469 pub const MSR_P4_CRU_ESCR4: ::std::os::raw::c_uint = 0x000003e0; 470 pub const MSR_P4_CRU_ESCR5: ::std::os::raw::c_uint = 0x000003e1; 471 pub const MSR_P4_DAC_ESCR0: ::std::os::raw::c_uint = 0x000003a8; 472 pub const MSR_P4_DAC_ESCR1: ::std::os::raw::c_uint = 0x000003a9; 473 pub const MSR_P4_FIRM_ESCR0: ::std::os::raw::c_uint = 0x000003a4; 474 pub const MSR_P4_FIRM_ESCR1: ::std::os::raw::c_uint = 0x000003a5; 475 pub const MSR_P4_FLAME_ESCR0: ::std::os::raw::c_uint = 0x000003a6; 476 pub const MSR_P4_FLAME_ESCR1: ::std::os::raw::c_uint = 0x000003a7; 477 pub const MSR_P4_FSB_ESCR0: ::std::os::raw::c_uint = 0x000003a2; 478 pub const MSR_P4_FSB_ESCR1: ::std::os::raw::c_uint = 0x000003a3; 479 pub const MSR_P4_IQ_ESCR0: ::std::os::raw::c_uint = 0x000003ba; 480 pub const MSR_P4_IQ_ESCR1: ::std::os::raw::c_uint = 0x000003bb; 481 pub const MSR_P4_IS_ESCR0: ::std::os::raw::c_uint = 0x000003b4; 482 pub const MSR_P4_IS_ESCR1: ::std::os::raw::c_uint = 0x000003b5; 483 pub const MSR_P4_ITLB_ESCR0: ::std::os::raw::c_uint = 0x000003b6; 484 pub const MSR_P4_ITLB_ESCR1: ::std::os::raw::c_uint = 0x000003b7; 485 pub const MSR_P4_IX_ESCR0: ::std::os::raw::c_uint = 0x000003c8; 486 pub const MSR_P4_IX_ESCR1: ::std::os::raw::c_uint = 0x000003c9; 487 pub const MSR_P4_MOB_ESCR0: ::std::os::raw::c_uint = 0x000003aa; 488 pub const MSR_P4_MOB_ESCR1: ::std::os::raw::c_uint = 0x000003ab; 489 pub const MSR_P4_MS_ESCR0: ::std::os::raw::c_uint = 0x000003c0; 490 pub const MSR_P4_MS_ESCR1: ::std::os::raw::c_uint = 0x000003c1; 491 pub const MSR_P4_PMH_ESCR0: ::std::os::raw::c_uint = 0x000003ac; 492 pub const MSR_P4_PMH_ESCR1: ::std::os::raw::c_uint = 0x000003ad; 493 pub const MSR_P4_RAT_ESCR0: ::std::os::raw::c_uint = 0x000003bc; 494 pub const MSR_P4_RAT_ESCR1: ::std::os::raw::c_uint = 0x000003bd; 495 pub const MSR_P4_SAAT_ESCR0: ::std::os::raw::c_uint = 0x000003ae; 496 pub const MSR_P4_SAAT_ESCR1: ::std::os::raw::c_uint = 0x000003af; 497 pub const MSR_P4_SSU_ESCR0: ::std::os::raw::c_uint = 0x000003be; 498 pub const MSR_P4_SSU_ESCR1: ::std::os::raw::c_uint = 0x000003bf; 499 pub const MSR_P4_TBPU_ESCR0: ::std::os::raw::c_uint = 0x000003c2; 500 pub const MSR_P4_TBPU_ESCR1: ::std::os::raw::c_uint = 0x000003c3; 501 pub const MSR_P4_TC_ESCR0: ::std::os::raw::c_uint = 0x000003c4; 502 pub const MSR_P4_TC_ESCR1: ::std::os::raw::c_uint = 0x000003c5; 503 pub const MSR_P4_U2L_ESCR0: ::std::os::raw::c_uint = 0x000003b0; 504 pub const MSR_P4_U2L_ESCR1: ::std::os::raw::c_uint = 0x000003b1; 505 pub const MSR_P4_PEBS_MATRIX_VERT: ::std::os::raw::c_uint = 0x000003f2; 506 pub const MSR_CORE_PERF_FIXED_CTR0: ::std::os::raw::c_uint = 0x00000309; 507 pub const MSR_CORE_PERF_FIXED_CTR1: ::std::os::raw::c_uint = 0x0000030a; 508 pub const MSR_CORE_PERF_FIXED_CTR2: ::std::os::raw::c_uint = 0x0000030b; 509 pub const MSR_CORE_PERF_FIXED_CTR_CTRL: ::std::os::raw::c_uint = 0x0000038d; 510 pub const MSR_CORE_PERF_GLOBAL_STATUS: ::std::os::raw::c_uint = 0x0000038e; 511 pub const MSR_CORE_PERF_GLOBAL_CTRL: ::std::os::raw::c_uint = 0x0000038f; 512 pub const MSR_CORE_PERF_GLOBAL_OVF_CTRL: ::std::os::raw::c_uint = 0x00000390; 513 pub const MSR_GEODE_BUSCONT_CONF0: ::std::os::raw::c_uint = 0x00001900; 514 pub const MSR_IA32_VMX_BASIC: ::std::os::raw::c_uint = 0x00000480; 515 pub const MSR_IA32_VMX_PINBASED_CTLS: ::std::os::raw::c_uint = 0x00000481; 516 pub const MSR_IA32_VMX_PROCBASED_CTLS: ::std::os::raw::c_uint = 0x00000482; 517 pub const MSR_IA32_VMX_EXIT_CTLS: ::std::os::raw::c_uint = 0x00000483; 518 pub const MSR_IA32_VMX_ENTRY_CTLS: ::std::os::raw::c_uint = 0x00000484; 519 pub const MSR_IA32_VMX_MISC: ::std::os::raw::c_uint = 0x00000485; 520 pub const MSR_IA32_VMX_CR0_FIXED0: ::std::os::raw::c_uint = 0x00000486; 521 pub const MSR_IA32_VMX_CR0_FIXED1: ::std::os::raw::c_uint = 0x00000487; 522 pub const MSR_IA32_VMX_CR4_FIXED0: ::std::os::raw::c_uint = 0x00000488; 523 pub const MSR_IA32_VMX_CR4_FIXED1: ::std::os::raw::c_uint = 0x00000489; 524 pub const MSR_IA32_VMX_VMCS_ENUM: ::std::os::raw::c_uint = 0x0000048a; 525 pub const MSR_IA32_VMX_PROCBASED_CTLS2: ::std::os::raw::c_uint = 0x0000048b; 526 pub const MSR_IA32_VMX_EPT_VPID_CAP: ::std::os::raw::c_uint = 0x0000048c; 527 pub const MSR_IA32_VMX_TRUE_PINBASED_CTLS: ::std::os::raw::c_uint = 0x0000048d; 528 pub const MSR_IA32_VMX_TRUE_PROCBASED_CTLS: ::std::os::raw::c_uint = 0x0000048e; 529 pub const MSR_IA32_VMX_TRUE_EXIT_CTLS: ::std::os::raw::c_uint = 0x0000048f; 530 pub const MSR_IA32_VMX_TRUE_ENTRY_CTLS: ::std::os::raw::c_uint = 0x00000490; 531 pub const MSR_IA32_VMX_VMFUNC: ::std::os::raw::c_uint = 0x00000491; 532 pub const VMX_BASIC_VMCS_SIZE_SHIFT: ::std::os::raw::c_uint = 0x00000020; 533 pub const VMX_BASIC_TRUE_CTLS: ::std::os::raw::c_ulonglong = 0x80000000000000; 534 pub const VMX_BASIC_64: ::std::os::raw::c_ulonglong = 0x1000000000000; 535 pub const VMX_BASIC_MEM_TYPE_SHIFT: ::std::os::raw::c_uint = 0x00000032; 536 pub const VMX_BASIC_MEM_TYPE_MASK: ::std::os::raw::c_ulonglong = 0x3c000000000000; 537 pub const VMX_BASIC_MEM_TYPE_WB: ::std::os::raw::c_uint = 0x00000006; 538 pub const VMX_BASIC_INOUT: ::std::os::raw::c_ulonglong = 0x40000000000000; 539 pub const MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS: ::std::os::raw::c_uint = 0x20000000; 540 pub const MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE: ::std::os::raw::c_uint = 0x0000001f; 541 pub const MSR_VM_CR: ::std::os::raw::c_uint = 0xc0010114; 542 pub const MSR_VM_IGNNE: ::std::os::raw::c_uint = 0xc0010115; 543 pub const MSR_VM_HSAVE_PA: ::std::os::raw::c_uint = 0xc0010117; 544