| /external/pffft/simd/ |
| D | pf_altivec_float.h | 52 # define VZERO() ((vector float) vec_splat_u8(0)) macro
53 # define VMUL(a,b) vec_madd(a,b, VZERO())
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| D | pf_scalar_float.h | 61 static ALWAYS_INLINE(v4sf) VZERO() { in VZERO() function
169 # define VZERO() 0.f macro
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| D | pf_scalar_double.h | 61 static ALWAYS_INLINE(v4sf) VZERO() { in VZERO() function
169 # define VZERO() 0.0 macro
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| D | pf_sse1_float.h | 56 # define VZERO() _mm_setzero_ps() macro
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| D | pf_neon_float.h | 54 # define VZERO() vdupq_n_f32(0) macro
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| D | pf_avx_double.h | 65 # define VZERO() _mm256_setzero_pd() macro
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| D | pf_neon_double.h | 59 # define VZERO() _mm256_setzero_pd() macro
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| D | pf_sse2_double.h | 142 # define VZERO() mm256_setzero_pd() macro
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | use-sgpr-multiple-times.ll | 249 ; GCN-DAG: v_mov_b32_e32 v[[VZERO:[0-9]+]], 0{{$}}
253 …+:[0-9]+\]]], v{{\[}}[[VS1_SUB0]]:[[VS1_SUB1]]{{\]}}, [[SGPR0]], v{{\[}}[[VZERO]]:[[VK0_SUB1]]{{\]…
257 …+:[0-9]+\]]], [[SGPR0]], v{{\[}}[[VS1_SUB0]]:[[VS1_SUB1]]{{\]}}, v{{\[}}[[VZERO]]:[[VK1_SUB1]]{{\]…
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.h | 83 VZERO, enumerator
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| D | HexagonPatternsHVX.td | 36 def HexagonVZERO: SDNode<"HexagonISD::VZERO", SDTVecLeaf>;
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| D | HexagonISelLowering.cpp | 1718 case HexagonISD::VZERO: return "HexagonISD::VZERO"; in getTargetNodeName()
2516 return DAG.getNode(HexagonISD::VZERO, dl, Ty); in getZero()
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| D | HexagonISelDAGToDAGHVX.cpp | 945 case HexagonISD::VZERO: in selectVectorConstants()
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| /external/pffft/ |
| D | pffft_priv_impl.h | 1286 v4sf save = in[7], zero=VZERO(); in FUNC_REAL_FINALIZE()
1789 t = a0; u = a1; t.v = VZERO(); in FUNC_VALIDATE_SIMD_A()
1852 C.v = VZERO(); in FUNC_VALIDATE_SIMD_EX()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrVector.td | 61 def VZERO : InherentVRIa<"vzero", 0xE744, 0>;
1618 def : Pat<(f128 fpimm0), (VZERO)>;
1619 def : Pat<(f128 fpimmneg0), (WFLNXB (VZERO))>;
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| D | SystemZScheduleZ13.td | 1183 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VZERO$")>;
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| D | SystemZScheduleZ15.td | 1222 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VZERO$")>;
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| D | SystemZScheduleZ14.td | 1201 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VZERO$")>;
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrVector.td | 58 def VZERO : InherentVRIa<"vzero", 0xE744, 0>;
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| /external/capstone/arch/SystemZ/ |
| D | SystemZGenAsmWriter.inc | 4908 3172836U, // VZERO
7711 0U, // VZERO
10514 0U, // VZERO
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| D | SystemZGenDisassemblerTables.inc | 3014 /* 4225 */ MCD_OPC_Decode, 248, 20, 242, 1, // Opcode: VZERO
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrSSE.td | 7266 // VZERO - Zero YMM registers
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrSSE.td | 8157 // VZERO - Zero YMM registers
|