Searched refs:WIDTH_M1_SHIFT_ (Results 1 – 9 of 9) sorted by relevance
201 WIDTH_M1_SHIFT_ = 11, enumerator203 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_)
200 .addImm(((Width - 1) << AMDGPU::Hwreg::WIDTH_M1_SHIFT_) | in insertSetreg()251 AMDGPU::Hwreg::WIDTH_M1_SHIFT_) + in processBlockPhase1()
356 WIDTH_M1_SHIFT_ = 11, enumerator358 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_),
233 (31 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_))); in emitFlatScratchInit()237 (31 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_))); in emitFlatScratchInit()
1202 WidthM1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_; in getSegmentAperture()2054 (1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_); in toggleSPDenormMode()
4686 WidthM1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_; in getSegmentAperture()7728 (1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_); in LowerFDIV32()
749 ((Width - 1) << WIDTH_M1_SHIFT_); in encodeHwreg()759 Width = ((Val & WIDTH_M1_MASK_) >> WIDTH_M1_SHIFT_) + 1; in decodeHwreg()
867 const unsigned Width = ((SImm16 & WIDTH_M1_MASK_) >> WIDTH_M1_SHIFT_) + 1; in printHwreg()
1888 … Imm16Val = (HwReg.Id << ID_SHIFT_) | (Offset << OFFSET_SHIFT_) | ((Width-1) << WIDTH_M1_SHIFT_); in parseHwreg()