| /external/vixl/test/aarch32/ |
| D | test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc | 169 {NZCVFlag, 0xffffffff, 0xffffffff}, {ZVFlag, 0xffffffff, 0xffffffff},
171 {ZCFlag, 0x00007ffe, 0x00007ffe}, {ZVFlag, 0xffff8000, 0xffff8000},
175 {CVFlag, 0xfffffffd, 0xfffffffd}, {ZVFlag, 0x00007ffe, 0x00007ffe},
179 {NZVFlag, 0xffff8001, 0xffff8001}, {ZVFlag, 0xffffff81, 0xffffff81},
191 {ZVFlag, 0xffffffe0, 0xffffffe0}, {ZCFlag, 0x55555555, 0x55555555},
217 {ZVFlag, 0xaaaaaaaa, 0xaaaaaaaa}, {CFlag, 0x00000000, 0x00000000},
221 {ZVFlag, 0xfffffffd, 0xfffffffd}, {NZCFlag, 0x0000007e, 0x0000007e},
224 {NZCFlag, 0x7fffffff, 0x7fffffff}, {ZVFlag, 0xffff8002, 0xffff8002},
230 {ZVFlag, 0x7ffffffe, 0x7ffffffe}, {VFlag, 0x7ffffffd, 0x7ffffffd},
236 {NCFlag, 0x00007ffd, 0x00007ffd}, {ZVFlag, 0x0000007e, 0x0000007e},
[all …]
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| D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 202 {ZVFlag, 0xabababab, 0xabababab, 0xabababab},
237 {ZVFlag, 0xfffffffd, 0xfffffffd, 0xffffffe0},
244 {ZVFlag, 0x00007ffd, 0x00007ffd, 0xffffff80},
284 {ZVFlag, 0x7ffffffe, 0x7ffffffe, 0xfffffffd},
298 {ZVFlag, 0xffffffe0, 0xffffffe0, 0x55555555},
301 {ZVFlag, 0xaaaaaaaa, 0xaaaaaaaa, 0xfffffffd},
315 {ZVFlag, 0x0000007e, 0x0000007e, 0x0000007f},
327 {ZVFlag, 0xffff8001, 0xffff8001, 0x00007ffe},
338 {ZVFlag, 0xffff8002, 0xffff8002, 0xaaaaaaaa},
402 {ZVFlag, 0xfffffffd, 0xfffffffd, 0xffffff83},
[all …]
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| D | test-utils-aarch32.h | 71 const uint32_t ZVFlag = ZFlag | VFlag; variable
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| D | test-simulator-cond-rd-operand-const-a32.cc | 172 {ZVFlag, 0xabababab},
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| D | test-simulator-cond-rd-operand-imm16-t32.cc | 166 {ZVFlag, 0xabababab},
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| D | test-simulator-cond-rd-operand-const-t32.cc | 172 {ZVFlag, 0xabababab},
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| D | test-simulator-cond-rd-operand-rn-a32.cc | 179 {ZVFlag, 0xabababab, 0xabababab},
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| D | test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 173 {ZVFlag, 0xabababab, 0xabababab},
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| D | test-simulator-cond-rd-operand-rn-t32.cc | 179 {ZVFlag, 0xabababab, 0xabababab},
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| D | test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 173 {ZVFlag, 0xabababab, 0xabababab},
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| D | test-simulator-cond-rdlow-rnlow-rmlow-t32.cc | 170 {ZVFlag, 0xabababab, 0xabababab, 0xabababab},
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 175 {ZVFlag, 0xabababab, 0xabababab},
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 175 {ZVFlag, 0xabababab, 0xabababab},
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 175 {ZVFlag, 0xabababab, 0xabababab},
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc | 175 {ZVFlag, 0xabababab, 0xabababab},
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| D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 202 {ZVFlag, 0xabababab, 0xabababab, 0xabababab},
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| D | test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc | 176 {ZVFlag, 0xabababab, 0xabababab, 0xabababab},
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| D | test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc | 176 {ZVFlag, 0xabababab, 0xabababab, 0xabababab},
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| D | test-simulator-cond-rd-rn-t32.cc | 172 {ZVFlag, 0xabababab, 0xabababab},
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| D | test-simulator-cond-rd-rn-a32.cc | 172 {ZVFlag, 0xabababab, 0xabababab},
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| D | test-simulator-cond-rdlow-operand-imm8-t32.cc | 167 {ZVFlag, 0xabababab},
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| D | test-simulator-cond-rd-rn-operand-const-a32.cc | 186 {ZVFlag, 0xabababab, 0xabababab},
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 190 {ZVFlag, 0xabababab, 0xabababab, 0xabababab},
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 190 {ZVFlag, 0xabababab, 0xabababab, 0xabababab},
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| /external/vixl/test/aarch64/ |
| D | test-disasm-fp-aarch64.cc | 219 COMPARE(fccmp(h10, h11, ZVFlag, ne), "fccmp h10, h11, #nZcV, ne"); in TEST()
223 COMPARE(fccmp(s2, s3, ZVFlag, ne), "fccmp s2, s3, #nZcV, ne"); in TEST()
235 COMPARE(fccmpe(h10, h11, ZVFlag, ne), "fccmpe h10, h11, #nZcV, ne"); in TEST()
239 COMPARE(fccmpe(s2, s3, ZVFlag, ne), "fccmpe s2, s3, #nZcV, ne"); in TEST()
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