| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenMCPseudoLowering.inc | 20 TmpInst.addOperand(MCOp);
22 TmpInst.addOperand(MCOperand::createImm(14));
23 TmpInst.addOperand(MCOperand::createReg(0));
33 TmpInst.addOperand(MCOp);
36 TmpInst.addOperand(MCOp);
39 TmpInst.addOperand(MCOp);
41 TmpInst.addOperand(MCOp);
44 TmpInst.addOperand(MCOp);
48 TmpInst.addOperand(MCOp);
58 TmpInst.addOperand(MCOp);
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCPseudoLowering.inc | 20 TmpInst.addOperand(MCOp);
23 TmpInst.addOperand(MCOp);
26 TmpInst.addOperand(MCOp);
36 TmpInst.addOperand(MCOp);
39 TmpInst.addOperand(MCOp);
42 TmpInst.addOperand(MCOp);
52 TmpInst.addOperand(MCOp);
55 TmpInst.addOperand(MCOp);
58 TmpInst.addOperand(MCOp);
67 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
[all …]
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 577 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF()
583 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF()
617 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
620 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
622 MI.addOperand(MCOperand::createImm(Imm)); in DecodeAddiGroupBranch()
637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
643 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
645 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
649 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 622 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF()
628 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF()
638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
640 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
642 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATIMMR6()
652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
654 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
656 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATI()
690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
693 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 415 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); in addRegGPRCOperands()
420 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); in addRegGPRCNoR0Operands()
425 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); in addRegG8RCOperands()
430 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); in addRegG8RCNoX0Operands()
449 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF4RCOperands()
454 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF8RCOperands()
459 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()])); in addRegVFRCOperands()
464 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); in addRegVRRCOperands()
469 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); in addRegVSRCOperands()
474 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); in addRegVSFRCOperands()
[all …]
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 1742 Inst.addOperand(MCOperand::createImm(0)); in addExpr()
1744 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addExpr()
1746 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr()
1761 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
1763 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands()
1768 Inst.addOperand(MCOperand::createImm(getCoproc())); in addCoprocNumOperands()
1773 Inst.addOperand(MCOperand::createImm(getCoproc())); in addCoprocRegOperands()
1778 Inst.addOperand(MCOperand::createImm(CoprocOption.Val)); in addCoprocOptionOperands()
1783 Inst.addOperand(MCOperand::createImm(ITMask.Mask)); in addITMaskOperands()
1788 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/RISCV/ |
| D | RISCVGenCompressInstEmitter.inc | 150 OutInst.addOperand(MI.getOperand(0));
152 OutInst.addOperand(MI.getOperand(2));
163 OutInst.addOperand(MI.getOperand(0));
165 OutInst.addOperand(MI.getOperand(1));
176 OutInst.addOperand(MI.getOperand(1));
178 OutInst.addOperand(MI.getOperand(1));
180 OutInst.addOperand(MI.getOperand(2));
191 OutInst.addOperand(MI.getOperand(2));
193 OutInst.addOperand(MI.getOperand(2));
195 OutInst.addOperand(MI.getOperand(1));
[all …]
|
| D | RISCVGenMCPseudoLowering.inc | 19 TmpInst.addOperand(MCOperand::createReg(RISCV::X0));
22 TmpInst.addOperand(MCOp);
31 TmpInst.addOperand(MCOperand::createReg(RISCV::X0));
34 TmpInst.addOperand(MCOp);
37 TmpInst.addOperand(MCOp);
46 TmpInst.addOperand(MCOperand::createReg(RISCV::X1));
49 TmpInst.addOperand(MCOp);
51 TmpInst.addOperand(MCOperand::createImm(0));
60 TmpInst.addOperand(MCOperand::createReg(RISCV::X0));
62 TmpInst.addOperand(MCOperand::createReg(RISCV::X1));
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 246 ITInst.addOperand(MCOperand::createImm(ITState.Cond)); in flushPendingInstructions()
247 ITInst.addOperand(MCOperand::createImm(ITState.Mask)); in flushPendingInstructions()
2325 Inst.addOperand(MCOperand::createImm(0)); in addExpr()
2327 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addExpr()
2329 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr()
2344 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
2346 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands()
2351 Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred()))); in addVPTPredNOperands()
2353 Inst.addOperand(MCOperand::createReg(RegNum)); in addVPTPredNOperands()
2370 Inst.addOperand(MCOperand::createReg(RegNum)); in addVPTPredROperands()
[all …]
|
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 557 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); in addRegGPRCOperands()
562 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); in addRegGPRCNoR0Operands()
567 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); in addRegG8RCOperands()
572 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); in addRegG8RCNoX0Operands()
591 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF4RCOperands()
596 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF8RCOperands()
601 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); in addRegVRRCOperands()
606 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); in addRegVSRCOperands()
611 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); in addRegVSFRCOperands()
616 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()])); in addRegVSSRCOperands()
[all …]
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 222 CompoundInsn->addOperand(Rt); in getCompoundInsn()
223 CompoundInsn->addOperand(L.getOperand(1)); // Immediate in getCompoundInsn()
224 CompoundInsn->addOperand(R.getOperand(0)); // Jump target in getCompoundInsn()
234 CompoundInsn->addOperand(Rt); in getCompoundInsn()
235 CompoundInsn->addOperand(Rs); in getCompoundInsn()
236 CompoundInsn->addOperand(R.getOperand(0)); // Jump target. in getCompoundInsn()
248 CompoundInsn->addOperand(Rs); in getCompoundInsn()
249 CompoundInsn->addOperand(Rt); in getCompoundInsn()
250 CompoundInsn->addOperand(R.getOperand(1)); in getCompoundInsn()
261 CompoundInsn->addOperand(Rs); in getCompoundInsn()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 252 T.addOperand(Inst.getOperand(i)); in ScaleVectorOffset()
260 T.addOperand(MCOperand::createExpr(NewHE)); in ScaleVectorOffset()
284 Inst.addOperand(Reg); in HexagonProcessInstruction()
285 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
286 Inst.addOperand(S16); in HexagonProcessInstruction()
293 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
300 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
307 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
314 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
321 Inst.addOperand(MCOperand::createExpr(C255)); in HexagonProcessInstruction()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 215 CompoundInsn->addOperand(Rt); in getCompoundInsn()
216 CompoundInsn->addOperand(L.getOperand(1)); // Immediate in getCompoundInsn()
217 CompoundInsn->addOperand(R.getOperand(0)); // Jump target in getCompoundInsn()
227 CompoundInsn->addOperand(Rt); in getCompoundInsn()
228 CompoundInsn->addOperand(Rs); in getCompoundInsn()
229 CompoundInsn->addOperand(R.getOperand(0)); // Jump target. in getCompoundInsn()
241 CompoundInsn->addOperand(Rs); in getCompoundInsn()
242 CompoundInsn->addOperand(Rt); in getCompoundInsn()
243 CompoundInsn->addOperand(R.getOperand(1)); in getCompoundInsn()
254 CompoundInsn->addOperand(Rs); in getCompoundInsn()
[all …]
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 271 Inst.addOperand(Reg); in HexagonProcessInstruction()
272 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
273 Inst.addOperand(S16); in HexagonProcessInstruction()
290 TmpInst.addOperand(Reg); in HexagonProcessInstruction()
291 TmpInst.addOperand(MCOperand::createExpr( in HexagonProcessInstruction()
309 TmpInst.addOperand(Reg); in HexagonProcessInstruction()
310 TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( in HexagonProcessInstruction()
322 MappedInst.addOperand(Ps); in HexagonProcessInstruction()
385 TmpInst.addOperand(MappedInst.getOperand(0)); in HexagonProcessInstruction()
386 TmpInst.addOperand(MappedInst.getOperand(1)); in HexagonProcessInstruction()
[all …]
|
| /external/llvm/include/llvm/MC/ |
| D | MCInstBuilder.h | 33 Inst.addOperand(MCOperand::createReg(Reg)); in addReg()
39 Inst.addOperand(MCOperand::createImm(Val)); in addImm()
45 Inst.addOperand(MCOperand::createFPImm(Val)); in addFPImm()
51 Inst.addOperand(MCOperand::createExpr(Val)); in addExpr()
57 Inst.addOperand(MCOperand::createInst(Val)); in addInst()
62 MCInstBuilder &addOperand(const MCOperand &Op) { in addOperand() function
63 Inst.addOperand(Op); in addOperand()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCInstBuilder.h | 32 Inst.addOperand(MCOperand::createReg(Reg)); in addReg()
38 Inst.addOperand(MCOperand::createImm(Val)); in addImm()
44 Inst.addOperand(MCOperand::createFPImm(Val)); in addFPImm()
50 Inst.addOperand(MCOperand::createExpr(Val)); in addExpr()
56 Inst.addOperand(MCOperand::createInst(Val)); in addInst()
61 MCInstBuilder &addOperand(const MCOperand &Op) { in addOperand() function
62 Inst.addOperand(Op); in addOperand()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 67 Inst.addOperand(MCOperand::createImm(Offset)); in DecodePCRel24BranchTarget()
78 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); in decodeRegisterClass()
182 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
190 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
213 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
224 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp))); in decodeMemRIOperands()
225 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
241 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands()
245 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2))); in decodeMemRIXOperands()
246 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 88 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
174 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
182 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
256 Inst.addOperand(MCOperand::createImm(Value)); in decodePCDBLOperand()
296 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
297 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDAddr12Operand()
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
307 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp))); in decodeBDAddr20Operand()
317 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
318 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDXAddr12Operand()
[all …]
|
| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 83 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
157 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
165 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
245 Inst.addOperand(MCOperand::createImm(Value)); in decodePCDBLOperand()
273 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
274 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDAddr12Operand()
283 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
284 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp))); in decodeBDAddr20Operand()
294 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
295 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDXAddr12Operand()
[all …]
|
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 73 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
88 MI->addOperand(*MF, MachineOperand::CreateImm(Val)); in addImm()
93 MI->addOperand(*MF, MachineOperand::CreateCImm(Val)); in addCImm()
98 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val)); in addFPImm()
104 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
109 MI->addOperand(*MF, MachineOperand::CreateFI(Idx)); in addFrameIndex()
116 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
122 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
129 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
136 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
[all …]
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AsmPrinter.cpp | 435 MOVI.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
436 MOVI.addOperand(MCOperand::createImm(0)); in EmitFMov0()
444 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
445 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in EmitFMov0()
449 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
450 FMov.addOperand(MCOperand::createReg(AArch64::XZR)); in EmitFMov0()
494 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
503 TmpInst.addOperand(Dest); in EmitInstruction()
527 Adrp.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
528 Adrp.addOperand(SymTLSDesc); in EmitInstruction()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 92 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
123 MI->addOperand(*MF, MachineOperand::CreateImm(Val)); in addImm()
128 MI->addOperand(*MF, MachineOperand::CreateCImm(Val)); in addCImm()
133 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val)); in addFPImm()
139 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
144 MI->addOperand(*MF, MachineOperand::CreateFI(Idx)); in addFrameIndex()
151 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
157 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
164 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
171 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.cpp | 38 NopInst.addOperand(MCOperand::createImm(0)); in getNoop()
39 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNoop()
40 NopInst.addOperand(MCOperand::createReg(0)); in getNoop()
43 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoop()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoop()
45 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNoop()
46 NopInst.addOperand(MCOperand::createReg(0)); in getNoop()
47 NopInst.addOperand(MCOperand::createReg(0)); in getNoop()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.cpp | 39 NopInst.addOperand(MCOperand::createImm(0)); in getNoopForMachoTarget()
40 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNoopForMachoTarget()
41 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoopForMachoTarget()
45 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoopForMachoTarget()
46 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNoopForMachoTarget()
47 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
48 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
|
| /external/llvm/lib/Target/Lanai/Disassembler/ |
| D | LanaiDisassembler.cpp | 126 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust()
169 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
178 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRiMemoryValue()
180 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); in decodeRiMemoryValue()
190 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
192 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
202 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeSplsValue()
204 Inst.addOperand(MCOperand::createImm(SignExtend32<10>(Offset))); in decodeSplsValue()
222 MI.addOperand(MCOperand::createImm(Insn)); in decodeBranch()
229 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); in decodeShiftImm()
[all …]
|