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Searched refs:align_u64 (Results 1 – 15 of 15) sorted by relevance

/external/mesa3d/src/intel/vulkan/
Danv_intel.c82 VkDeviceSize aligned_image_size = align_u64(image->size, 4096); in anv_CreateDmaBufImageINTEL()
Danv_allocator.c1627 size = align_u64(size, 4096); in anv_device_alloc_bo()
1636 size = align_u64(size, 64 * 1024); in anv_device_alloc_bo()
1639 ccs_size = align_u64(DIV_ROUND_UP(size, GEN_AUX_MAP_GEN12_CCS_SCALE), 4096); in anv_device_alloc_bo()
Danv_image.c336 image->planes[plane].size = align_u64(image->planes[plane].size, 4096); in add_aux_state_tracking_buffer()
337 image->size = align_u64(image->size, 4096); in add_aux_state_tracking_buffer()
Danv_device.c3453 align_u64(pAllocateInfo->allocationSize, 4096); in anv_AllocateMemory()
3859 map_size = align_u64(map_size, 4096); in anv_MapMemory()
3975 pMemoryRequirements->size = align_u64(buffer->size, 4); in anv_GetBufferMemoryRequirements()
Danv_private.h273 align_u64(uint64_t v, uint64_t a) in align_u64() function
591 size_t offset = align_u64(ma->size, align); in _anv_multialloc_add()
Danv_descriptor_set.c1488 bind_range = align_u64(bind_range, ANV_UBO_ALIGNMENT); in anv_descriptor_set_write_buffer()
DgenX_cmd_buffer.c522 end_offset_B = align_u64(end_offset_B, 64 * 1024); in anv_image_init_aux_tt()
4932 bound->end = align_u64(bound->end, 64); in genX()
/external/igt-gpu-tools/tools/
Daubdump.c320 align_u64(uint64_t v, uint64_t a) in align_u64() function
390 uint64_t end_aligned = align_u64(end, 4096); in gen8_emit_ggtt_pte_for_range()
/external/mesa3d/docs/relnotes/
D20.0.5.rst124 - anv/image: Use align_u64 for image offsets
D20.1.0.rst2431 - anv/image: Use align_u64 for image offsets
/external/mesa3d/src/amd/vulkan/
Dradv_descriptor_set.c378 if (size && !align_u64(size, descriptor_alignment)) { in radv_GetDescriptorSetLayoutSupport()
381 size = align_u64(size, descriptor_alignment); in radv_GetDescriptorSetLayoutSupport()
Dradv_debug.c798 uint64_t offset = align_u64(s->bo_offset + s->code_size, 256); in radv_get_faulty_shader()
Dradv_shader.c798 offset = align_u64(s->bo_offset + s->code_size, 256); in radv_alloc_shader_memory()
Dradv_private.h115 align_u64(uint64_t v, uint64_t a) in align_u64() function
Dradv_device.c5326 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096); in radv_alloc_memory()