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/external/llvm/test/MC/Disassembler/Hexagon/
Dxtype_shift.txt10 # CHECK: r17:16 = asl(r21:20, #31)
16 # CHECK: r17 = asl(r21, #31)
24 # CHECK: r17:16 -= asl(r21:20, #31)
30 # CHECK: r17:16 += asl(r21:20, #31)
36 # CHECK: r17 -= asl(r21, #31)
42 # CHECK: r17 += asl(r21, #31)
44 # CHECK: r17 = add(#21, asl(r17, #23))
46 # CHECK: r17 = sub(#21, asl(r17, #23))
62 # CHECK: r17:16 &= asl(r21:20, #31)
68 # CHECK: r17:16 |= asl(r21:20, #31)
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/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_shift.ll22 declare i64 @llvm.hexagon.S2.asl.i.p(i64, i32)
24 %z = call i64 @llvm.hexagon.S2.asl.i.p(i64 %a, i32 0)
27 ; CHECK: = asl({{.*}}, #0)
43 declare i32 @llvm.hexagon.S2.asl.i.r(i32, i32)
45 %z = call i32 @llvm.hexagon.S2.asl.i.r(i32 %a, i32 0)
48 ; CHECK: = asl({{.*}}, #0)
65 declare i64 @llvm.hexagon.S2.asl.i.p.nac(i64, i64, i32)
67 %z = call i64 @llvm.hexagon.S2.asl.i.p.nac(i64 %a, i64 %b, i32 0)
70 ; CHECK: -= asl({{.*}}, #0)
86 declare i64 @llvm.hexagon.S2.asl.i.p.acc(i64, i64, i32)
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/external/llvm/test/CodeGen/Hexagon/vect/
Dvect-shift-imm.ll21 %0 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %x, i32 9)
24 %3 = tail call i64 @llvm.hexagon.S2.asl.i.vh(i64 %x, i32 6)
35 declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) nounwind readnone
38 declare i64 @llvm.hexagon.S2.asl.i.vh(i64, i32) nounwind readnone
Dvect-vshifts.ll24 %9 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %8, i32 1)
48 %20 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %19, i32 %gb)
77 %31 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %30, i32 %gb)
106 %42 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %41, i32 %gb)
135 %53 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %52, i32 %gb)
164 %64 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %63, i32 %gb)
193 %75 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %74, i32 %gb)
222 %86 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %85, i32 %gb)
251 %97 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %96, i32 %gb)
264 declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) #1
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/external/webrtc/common_audio/signal_processing/
Dcomplex_bit_reverse_arm.S33 mov r1, r3, asl r1 @ n = 1 << stages;
55 mov r12, r4, asl #2
71 add r4, r3, r4, asl #1
/external/llvm/test/CodeGen/Hexagon/
Dinsert4.ll46 %3 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %2, i32 -25)
51 %6 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %5, i32 -25)
58 %10 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %9, i32 -25)
63 %13 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %12, i32 -25)
101 declare i64 @llvm.hexagon.S2.asl.r.p(i64, i32) #1
Dhwloop-crit-edge.ll13 %2 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %1, i32 -13)
31 %8 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %7, i32 -13)
53 declare i64 @llvm.hexagon.S2.asl.r.p(i64, i32) #1
Dalu64.ll436 ; CHECK: = and(#1, asl(r0, #2))
439 %0 = tail call i32 @llvm.hexagon.S4.andi.asl.ri(i32 1, i32 %Rs, i32 2)
444 ; CHECK: = or(#1, asl(r0, #2))
447 %0 = tail call i32 @llvm.hexagon.S4.ori.asl.ri(i32 1, i32 %Rs, i32 2)
452 ; CHECK: = add(#1, asl(r0, #2))
455 %0 = tail call i32 @llvm.hexagon.S4.addi.asl.ri(i32 1, i32 %Rs, i32 2)
460 ; CHECK: = sub(#1, asl(r0, #2))
463 %0 = tail call i32 @llvm.hexagon.S4.subi.asl.ri(i32 1, i32 %Rs, i32 2)
589 declare i32 @llvm.hexagon.S4.andi.asl.ri(i32, i32, i32) #1
590 declare i32 @llvm.hexagon.S4.ori.asl.ri(i32, i32, i32) #1
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Dstruct_args.ll3 ; CHECK: r{{[0-9]}}:{{[0-9]}} |= asl(r{{[0-9]}}:{{[0-9]}}, #32)
/external/strace/
Dmpers_test.sh61 long asl[3][5][7];
108 int${size}_t asl[3][5][7];
/external/clang/test/Sema/
Dformat-strings.c314 int asl_log(aslclient asl, aslmsg msg, int level, const char *format, ...) __attribute__((__format_…
315 void test_asl(aslclient asl) { in test_asl() argument
317 asl_log(asl, 0, 3, "Error: %m"); // no-warning in test_asl()
318 asl_log(asl, 0, 3, "Error: %W"); // expected-warning{{invalid conversion specifier 'W'}} in test_asl()
/external/clang/test/Analysis/
Dblocks.m48 int asl_log(aslclient asl, aslmsg msg, int level, const char *format, ...) __attribute__((__format_…
64 logQueue = dispatch_queue_create("com.mycompany.myproduct.asl", 0);
/external/llvm/lib/Target/ARM/
DREADME-Thumb.txt142 mov r1, r2, asl r0
143 ands r0, r3, r2, asl r0
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DREADME-Thumb.txt142 mov r1, r2, asl r0
143 ands r0, r3, r2, asl r0
/external/arm-trusted-firmware/include/drivers/
Dufs.h292 uint8_t asl; member
/external/clang/test/CodeGen/
Dbuiltins-ppc-vsx.c34 signed long asl[2] = { -1L, 2L }; variable
/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV4.td55 //Rxx^=asl(Rss,Rt)
DHexagonInstrInfo.td4043 def S2_asl_i_r : T_S2op_shift <"asl", 0b000, 0b010, shl>;
4048 def S2_asl_i_r_sat : T_S2op_2_ii <"asl", 0b010, 0b010, 1>;
4428 def S2_asl_i_p : S_2OpInstImmI6<"asl", shl, 0b010>;
5113 // Rx[+-&|^]=asl(Rs,#u5)
5143 // Rx[+-&|^]=asl(Rs,Rt)
5171 // Rxx[+-&|^]=asl(Rss,#u6)
5200 // Rxx[+-&|^]=asl(Rss,Rt)
5257 defm S2_asl : xtype_imm_acc<"asl", shl, 0b10>,
5258 xtype_xor_imm_acc<"asl", shl, 0b10>;
5284 defm S2_asl : xtype_reg_acc<"asl", shl, 0b10>;
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/external/google-breakpad/src/client/ios/
DBreakpadController.mm33 #include <asl.h>
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV5.td63 //Rxx^=asl(Rss,Rt)
/external/llvm/
DCREDITS.TXT224 E: asl@math.spbu.ru
/external/swiftshader/third_party/llvm-subzero/
DCREDITS.TXT223 E: asl@math.spbu.ru
/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/test/calendar/
DIBMCalendarTest.java540 Date asl = cal.getTime(); in TestLeapFieldDifference() local
543 int d2 = cal.fieldDifference(asl, Calendar.DAY_OF_MONTH); in TestLeapFieldDifference()
/external/icu/android_icu4j/src/main/tests/android/icu/dev/test/calendar/
DIBMCalendarTest.java543 Date asl = cal.getTime(); in TestLeapFieldDifference() local
546 int d2 = cal.fieldDifference(asl, Calendar.DAY_OF_MONTH); in TestLeapFieldDifference()
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen1336 hexagon_S2_asl_i_p, // llvm.hexagon.S2.asl.i.p
1337 hexagon_S2_asl_i_p_acc, // llvm.hexagon.S2.asl.i.p.acc
1338 hexagon_S2_asl_i_p_and, // llvm.hexagon.S2.asl.i.p.and
1339 hexagon_S2_asl_i_p_nac, // llvm.hexagon.S2.asl.i.p.nac
1340 hexagon_S2_asl_i_p_or, // llvm.hexagon.S2.asl.i.p.or
1341 hexagon_S2_asl_i_p_xacc, // llvm.hexagon.S2.asl.i.p.xacc
1342 hexagon_S2_asl_i_r, // llvm.hexagon.S2.asl.i.r
1343 hexagon_S2_asl_i_r_acc, // llvm.hexagon.S2.asl.i.r.acc
1344 hexagon_S2_asl_i_r_and, // llvm.hexagon.S2.asl.i.r.and
1345 hexagon_S2_asl_i_r_nac, // llvm.hexagon.S2.asl.i.r.nac
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