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Searched refs:b10 (Results 1 – 25 of 196) sorted by relevance

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/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td312 def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>;
313 def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>;
314 def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>;
315 def : ROSysReg<"OSLSR_EL1", 0b10, 0b000, 0b0001, 0b0001, 0b100>;
316 def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b10, 0b000, 0b0111, 0b1110, 0b110>;
367 def : ROSysReg<"TRCSTATR", 0b10, 0b001, 0b0000, 0b0011, 0b000>;
368 def : ROSysReg<"TRCIDR8", 0b10, 0b001, 0b0000, 0b0000, 0b110>;
369 def : ROSysReg<"TRCIDR9", 0b10, 0b001, 0b0000, 0b0001, 0b110>;
370 def : ROSysReg<"TRCIDR10", 0b10, 0b001, 0b0000, 0b0010, 0b110>;
371 def : ROSysReg<"TRCIDR11", 0b10, 0b001, 0b0000, 0b0011, 0b110>;
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/external/libaom/test/
Dtest_data_util.cmake178 "av1-1-b10-00-quantizer-00.ivf"
179 "av1-1-b10-00-quantizer-00.ivf.md5"
180 "av1-1-b10-00-quantizer-01.ivf"
181 "av1-1-b10-00-quantizer-01.ivf.md5"
182 "av1-1-b10-00-quantizer-02.ivf"
183 "av1-1-b10-00-quantizer-02.ivf.md5"
184 "av1-1-b10-00-quantizer-03.ivf"
185 "av1-1-b10-00-quantizer-03.ivf.md5"
186 "av1-1-b10-00-quantizer-04.ivf"
187 "av1-1-b10-00-quantizer-04.ivf.md5"
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Dtest-data.sha1407 9bbe8499796aa588ff02e313fb0d4349940d2fea *av1-1-b10-00-quantizer-00.ivf
408 36b402eedad2bacee8ac09acce44e2fc356dd80b *av1-1-b10-00-quantizer-00.ivf.md5
409 1d5e1d2827624f328020bf123df213bb175577e0 *av1-1-b10-00-quantizer-01.ivf
410 16c529be5502369e43ce9c6fe99a9709968e3daf *av1-1-b10-00-quantizer-01.ivf.md5
411 39abc20739242a8f05efd4b35d7603c8ad7ff45d *av1-1-b10-00-quantizer-02.ivf
412 81faa72c3d43b003966fe09ffaae51b07b1059be *av1-1-b10-00-quantizer-02.ivf.md5
413 92ebf349b803333a43824a83d997b8cf76f656f9 *av1-1-b10-00-quantizer-03.ivf
414 5e7556dc998cb8b506a43cc078e30802d7e600e6 *av1-1-b10-00-quantizer-03.ivf.md5
415 1c496177c66e49f2e3556af87ec67afb5060170b *av1-1-b10-00-quantizer-04.ivf
416 560fea4800a44fe19ed8d3e74f425bdbf1fb8abd *av1-1-b10-00-quantizer-04.ivf.md5
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td380 def : BTI<"j", 0b10>;
554 def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>;
555 def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>;
556 def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>;
557 def : ROSysReg<"OSLSR_EL1", 0b10, 0b000, 0b0001, 0b0001, 0b100>;
558 def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b10, 0b000, 0b0111, 0b1110, 0b110>;
619 def : ROSysReg<"TRCSTATR", 0b10, 0b001, 0b0000, 0b0011, 0b000>;
620 def : ROSysReg<"TRCIDR8", 0b10, 0b001, 0b0000, 0b0000, 0b110>;
621 def : ROSysReg<"TRCIDR9", 0b10, 0b001, 0b0000, 0b0001, 0b110>;
622 def : ROSysReg<"TRCIDR10", 0b10, 0b001, 0b0000, 0b0010, 0b110>;
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DAArch64SVEInstrInfo.td96 defm EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor", xor>;
134 defm AND_ZI : sve_int_log_imm<0b10, "and", "bic", and>;
137 defm SMIN_ZI : sve_int_arith_imm1<0b10, "smin", smin>;
221 defm FNMLA_ZPmZZ : sve_fp_3op_p_zds_a<0b10, "fnmla", int_aarch64_sve_fnmla>;
226 defm FNMAD_ZPmZZ : sve_fp_3op_p_zds_b<0b10, "fnmad", int_aarch64_sve_fnmad>;
282 defm UUNPKLO_ZZ : sve_int_perm_unpk<0b10, "uunpklo", AArch64uunpklo>;
294 def BRKPAS_PPzPP : sve_int_brkp<0b10, "brkpas">;
362 defm LD1RB_S_IMM : sve_mem_ld_dup<0b00, 0b10, "ld1rb", Z_s, ZPR32, uimm6s1>;
366 defm LD1RH_S_IMM : sve_mem_ld_dup<0b01, 0b10, "ld1rh", Z_s, ZPR32, uimm6s2>;
368 defm LD1RSH_D_IMM : sve_mem_ld_dup<0b10, 0b00, "ld1rsh", Z_d, ZPR64, uimm6s2>;
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DSVEInstrFormats.td282 def _S : sve_int_ptrue<0b10, opc, asm, PPR32, nxv4i1, op>;
452 def _S : sve_int_pfirst_next<0b10, opc, asm, PPR32>;
493 def _S : sve_int_count_r<0b10, opc, asm, GPR64z, PPR32, GPR64as32>;
521 def _S : sve_int_count_r<0b10, opc, asm, GPR32z, PPR32, GPR32z>;
538 def _S : sve_int_count_r<0b10, opc, asm, GPR64z, PPR32, GPR64z>;
576 def _S : sve_int_count_v<0b10, opc, asm, ZPR32, PPR32>;
604 let Inst{15-14} = 0b10;
615 def _S : sve_int_pcount_pred<0b10, opc, asm, PPR32>;
638 let Inst{21-20} = 0b10;
825 def _S : sve_int_perm_dup_r<0b10, asm, ZPR32, nxv4i32, GPR32sp, op>;
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/external/ComputeLibrary/src/cpu/kernels/gemm_matrix_mul/generic/neon/
Dimpl.cpp102 float16x8_t b10 = vld1q_f16(matrix_b + 0 + 1 * in_b_stride); in vector_matrix_multiply_f16() local
111 acc0 = vaddq_f16(acc0, vmulq_lane_f16(b10, a0l, 1)); in vector_matrix_multiply_f16()
122 b10 = vld1q_f16(matrix_b + 0 + 1 * in_b_stride); in vector_matrix_multiply_f16()
131 acc0 = vaddq_f16(acc0, vmulq_lane_f16(b10, a0l, 3)); in vector_matrix_multiply_f16()
304 float32x4_t b10 = vld1q_f32(matrix_b + 0 + 1 * in_b_stride); in vector_matrix_multiply_f32() local
322 acc0 = vmlaq_lane_f32(acc0, b10, a0l, 1); in vector_matrix_multiply_f32()
337 b10 = vld1q_f32(matrix_b + 0 + 1 * in_b_stride); in vector_matrix_multiply_f32()
347 acc0 = vmlaq_lane_f32(acc0, b10, a0l, 1); in vector_matrix_multiply_f32()
532 float32x4_t b10 = vld1q_f32(mtx_b1); in matrix_matrix_multiply_f32() local
554 acc01 = vmlaq_f32(acc01, b10, a0); in matrix_matrix_multiply_f32()
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/external/skia/src/core/
DSkMatrixInvert.cpp100 double b10 = a21 * a33 - a23 * a31; in SkInvert4x4Matrix() local
104 double determinant = b00 * b11 - b01 * b10 + b02 * b09 + b03 * b08 - b04 * b07 + b05 * b06; in SkInvert4x4Matrix()
117 b10 *= invdet; in SkInvert4x4Matrix()
120 outMatrix[0] = a11 * b11 - a12 * b10 + a13 * b09; in SkInvert4x4Matrix()
121 outMatrix[1] = a02 * b10 - a01 * b11 - a03 * b09; in SkInvert4x4Matrix()
128 outMatrix[8] = a10 * b10 - a11 * b08 + a13 * b06; in SkInvert4x4Matrix()
129 outMatrix[9] = a01 * b08 - a00 * b10 - a03 * b06; in SkInvert4x4Matrix()
/external/llvm/lib/Target/Sparc/
DSparcInstrVIS.td17 : F3_3<0b10, 0b110110, opfval, outs, ins, asmstr, pattern>;
186 def FHADDS : F3_3<0b10, 0b110100, 0b001100001,
189 def FHADDD : F3_3<0b10, 0b110100, 0b001100010,
192 def FHSUBS : F3_3<0b10, 0b110100, 0b001100101,
195 def FHSUBD : F3_3<0b10, 0b110100, 0b001100110,
207 def FNADDS : F3_3<0b10, 0b110100, 0b001010001,
210 def FNADDD : F3_3<0b10, 0b110100, 0b001010010,
213 def FNHADDS : F3_3<0b10, 0b110100, 0b001110001,
216 def FNHADDD : F3_3<0b10, 0b110100, 0b001110010,
220 def FNMULS : F3_3<0b10, 0b110100, 0b001011001,
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrVIS.td16 : F3_3<0b10, 0b110110, opfval, outs, ins, asmstr, pattern>;
185 def FHADDS : F3_3<0b10, 0b110100, 0b001100001,
188 def FHADDD : F3_3<0b10, 0b110100, 0b001100010,
191 def FHSUBS : F3_3<0b10, 0b110100, 0b001100101,
194 def FHSUBD : F3_3<0b10, 0b110100, 0b001100110,
206 def FNADDS : F3_3<0b10, 0b110100, 0b001010001,
209 def FNADDD : F3_3<0b10, 0b110100, 0b001010010,
212 def FNHADDS : F3_3<0b10, 0b110100, 0b001110001,
215 def FNHADDD : F3_3<0b10, 0b110100, 0b001110010,
219 def FNMULS : F3_3<0b10, 0b110100, 0b001011001,
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/external/capstone/suite/MC/AArch64/
Dneon-scalar-shift-imm.s.cs25 0xea,0x95,0x0b,0x5f = sqshrn b10, h15, #5
31 0xaa,0x9d,0x0e,0x5f = sqrshrn b10, h13, #2
34 0x8a,0x9d,0x0b,0x7f = uqrshrn b10, h12, #5
/external/llvm/test/MC/AArch64/
Dneon-scalar-shift-imm.s124 sqshrn b10, h15, #5
146 sqrshrn b10, h13, #2
157 uqrshrn b10, h12, #5
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td399 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
404 class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>;
409 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
414 class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>;
419 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
424 class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>;
433 class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>;
438 class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>;
443 class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>;
448 class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>;
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/external/webrtc/modules/desktop_capture/linux/wayland/
Dscreencast_portal.h48 kEmbedded = 0b10,
65 kPersistent = 0b10
129 kWindow = 0b10,
/external/eigen/Eigen/src/SparseLU/
DSparseLU_gemm_kernel.h74 Packet b00, b10, b20, b30, b01, b11, b21, b31; in sparselu_gemm() local
76 { b10 = pset1<Packet>(Bc0[1]); } in sparselu_gemm()
114 KMADD(c0, a1, b10, t0) \ in sparselu_gemm()
178 Packet b00, b10, b20, b30; in sparselu_gemm() local
180 b10 = pset1<Packet>(Bc0[1]); in sparselu_gemm()
210 KMADD(c0, a1, b10, t0) \ in sparselu_gemm()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td413 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
418 class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>;
423 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
428 class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>;
433 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
438 class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>;
447 class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>;
452 class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>;
457 class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>;
462 class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>;
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/external/cronet/third_party/abseil-cpp/absl/crc/internal/
Dnon_temporal_arm_intrinsics.h67 signed char b11, signed char b10, signed char b9, signed char b8, in _mm_set_epi8() argument
73 (int8_t)b8, (int8_t)b9, (int8_t)b10, (int8_t)b11, in _mm_set_epi8()
/external/angle/third_party/abseil-cpp/absl/crc/internal/
Dnon_temporal_arm_intrinsics.h67 signed char b11, signed char b10, signed char b9, signed char b8, in _mm_set_epi8() argument
73 (int8_t)b8, (int8_t)b9, (int8_t)b10, (int8_t)b11, in _mm_set_epi8()
/external/skia/modules/canvaskit/
Dmatrix.js348 var b10 = a21 * a33 - a23 * a31;
352 var det = b00 * b11 - b01 * b10 + b02 * b09 + b03 * b08 - b04 * b07 + b05 * b06;
371 b10 *= invdet;
376 a11 * b11 - a12 * b10 + a13 * b09,
378 a10 * b10 - a11 * b08 + a13 * b06,
381 a02 * b10 - a01 * b11 - a03 * b09,
383 a01 * b08 - a00 * b10 - a03 * b06,
/external/oj-libjdwp/src/share/classes/com/sun/tools/jdi/
DPacket.java110 short b10 = (short)(b[10] & 0xff); in fromByteArray() local
111 p.errorCode = (short)((b9 << 8) + (b10 << 0)); in fromByteArray()
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td667 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
675 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
695 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
703 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
712 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
720 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
740 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
748 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
756 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
781 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrNEON.td624 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
632 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
652 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
660 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
669 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
677 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
697 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
705 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
713 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
750 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
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/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td94 def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9Ext>;
278 def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>;
454 def A2_orir : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel;
500 let Inst{25-24} = !if(isHi, 0b10, 0b01);
1070 def A2_subh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 1>;
1074 def A2_addh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 0>;
1079 def A2_subh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 1>;
1083 def A2_addh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 0>;
1089 def A2_subh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 1>;
1095 def A2_addh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 0>;
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/external/igt-gpu-tools/lib/
Digt_edid.h51 STD_TIMING_5_4 = 0b10,
70 #define EDID_PT_SYNC_DIGITAL_COMPOSITE (0b10 << 3)
226 HDMI_VSDB_VIDEO_3D_STRUCT_MASK_PRESENT = 0b10 << 5,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoC.td220 : RVInst16CI<funct3, 0b10, (outs cls:$rd), (ins SP:$rs1, opnd:$imm),
226 : RVInst16CSS<funct3, 0b10, (outs), (ins cls:$rs2, SP:$rs1, opnd:$imm),
444 let Inst{11-10} = 0b10;
452 def C_OR : CS_ALU<0b100011, 0b10, "c.or" , GPRC>,
476 def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb),
513 def C_JR : RVInst16CR<0b1000, 0b10, (outs), (ins GPRNoX0:$rs1),
523 def C_MV : RVInst16CR<0b1000, 0b10, (outs GPRNoX0:$rs1), (ins GPRNoX0:$rs2),
528 def C_EBREAK : RVInst16CR<0b1001, 0b10, (outs), (ins), "c.ebreak", "">, Sched<[]>;
532 def C_JALR : RVInst16CR<0b1001, 0b10, (outs), (ins GPRNoX0:$rs1),
536 def C_ADD : RVInst16CR<0b1001, 0b10, (outs GPRNoX0:$rs1_wb),
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