Searched refs:ctl_val (Results 1 – 3 of 3) sorted by relevance
47 unsigned int ctl_val; in check_cpuxgpt_write_permission() local54 ctl_val = mmio_read_32(CTL_BASE); in check_cpuxgpt_write_permission()55 if (ctl_val & 1) { in check_cpuxgpt_write_permission()
337 uint32_t ctl_val; in load_infoframe() local340 ctl_val = INREG(ctl_reg); in load_infoframe()342 ctl_val &= ~DIP_CTL_BUFFER_INDEX; in load_infoframe()343 ctl_val |= type << 19; in load_infoframe()344 OUTREG(ctl_reg, ctl_val); in load_infoframe()345 ctl_val = INREG(ctl_reg); in load_infoframe()347 ctl_val &= ~DIP_CTL_ACCESS_ADDR; in load_infoframe()348 OUTREG(ctl_reg, ctl_val); in load_infoframe()351 ctl_val = INREG(ctl_reg); in load_infoframe()352 assert((ctl_val & DIP_CTL_ACCESS_ADDR) == i); in load_infoframe()[all …]
191 uint32_t ctl_val, voltage; in chal_sd_init() local252 ctl_val = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_init()254 ctl_val |= ((timeout_val & 0xf) << SD4_EMMC_TOP_CTRL1_DTCNT_SHIFT); in chal_sd_init()257 ctl_val); in chal_sd_init()291 ctl_val = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_init()293 handle->ctrl.version = ((ctl_val >> 16) & 0xFF); in chal_sd_init()423 uint32_t ctl_val; in chal_sd_config_bus_width() local431 ctl_val = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_config_bus_width()437 ctl_val &= ~SD_BUS_DATA_WIDTH_4BIT; in chal_sd_config_bus_width()438 ctl_val |= SD_BUS_DATA_WIDTH_8BIT; in chal_sd_config_bus_width()[all …]