| /external/llvm/test/CodeGen/X86/ |
| D | misched-aa-mmos.ll | 3 ; This generates a decw instruction, which has two MMOs, and an alias SU edge
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| D | lsr-wrap.ll | 7 ; CHECK: decw %
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| D | atomic_add.ll | 178 ; CHECK: decw
180 ; SLOW_INC-NOT: decw
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| D | atomic16.ll | 41 ; X64: decw
43 ; X32: decw
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| D | rd-mod-wr-eflags.ll | 97 ; CHECK: decw {{[0-9][0-9]*}}({{.*}})
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| D | atomic_mi.ll | 782 ; X64-NOT: decw
784 ; X32-NOT: decw
786 ; SLOW_INC-NOT: decw
|
| /external/ImageMagick/MagickCore/ |
| D | Make.com | 10 $if (f$trnlnm("X11") .eqs. "") then define/nolog X11 decw$include:
|
| /external/llvm/test/MC/X86/ |
| D | x86-16.s | 553 decw %ax
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| D | x86-32.s | 692 decw %ax
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| D | x86-64.s | 1037 decw %ax // CHECK: decw %ax # encoding: [0x66,0xff,0xc8] label
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| D | x86-32-coverage.s | 505 decw 0x7eed
|
| /external/ImageMagick/ |
| D | Magickshr.opt | 212 sys$share:decw$xlibshr.exe/share
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| /external/ImageMagick/coders/ |
| D | Make.com | 7 $if (f$trnlnm("X11") .eqs. "") then define/nolog X11 decw$include:
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| /external/llvm/test/MC/Disassembler/X86/ |
| D | x86-16.txt | 510 # CHECK: decw %ax
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| D | x86-64.txt | 215 # CHECK: decw %cx
|
| D | x86-32.txt | 709 # CHECK: decw %cx
|
| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 428 #define DEC_W(a) CHOICE(decw a, decw a, _WTOG dec a)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SVEInstrInfo.td | 854 defm DECW_XPiI : sve_int_pred_pattern_a<0b101, "decw">;
905 defm DECW_ZPiI : sve_int_countvlv<0b10101, "decw", ZPR32>;
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 4014 void decw(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
4017 void decw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
|
| D | assembler-sve-aarch64.cc | 450 V(decw, DECW_r_rs) \
520 V(decw, DEC, W) \
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| D | macro-assembler-aarch64.h | 4048 decw(rdn, pattern, multiplier);
4053 decw(zdn, pattern, multiplier);
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12494 "decp\004decw\003dmb\004drps\003dsb\003dup\004dupm\003eon\003eor\004eor3"
12608 "decw\006uqincb\006uqincd\006uqinch\006uqincp\006uqincw\006uqrshl\007uqr"
13498 …{ 944 /* decw */, AArch64::DECW_XPiI, Convert__Reg1_0__Tie0_1_1__imm_95_31__imm_95_1, AMFBS_HasSVE…
13499 …{ 944 /* decw */, AArch64::DECW_ZPiI, Convert__SVEVectorSReg1_0__Tie0_1_1__imm_95_31__imm_95_1, AM…
13500 …{ 944 /* decw */, AArch64::DECW_XPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1, AMFBS_Ha…
13501 …{ 944 /* decw */, AArch64::DECW_ZPiI, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1…
13502 …{ 944 /* decw */, AArch64::DECW_XPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161_3, AMFBS_…
13503 …{ 944 /* decw */, AArch64::DECW_ZPiI, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161…
20871 …{ 944 /* decw */, AArch64::DECW_XPiI, Convert__Reg1_0__Tie0_1_1__imm_95_31__imm_95_1, AMFBS_HasSVE…
20872 …{ 944 /* decw */, AArch64::DECW_ZPiI, Convert__SVEVectorSReg1_0__Tie0_1_1__imm_95_31__imm_95_1, AM…
[all …]
|
| /external/vixl/test/aarch64/ |
| D | test-api-movprfx-aarch64.cc | 1119 __ decw(z6.VnS(), SVE_ALL); in TEST() local
1416 __ decw(z4.VnS(), SVE_ALL); in TEST() local
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 7209 void decw(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1)
7216 void decw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1)
|
| /external/elfutils/tests/ |
| D | testfile44.expect.bz2 | 1testfile44.o: elf32-elf_i386
2
3Disassembly of section .text:
4
5 0 ... |