| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | radeon_screen.c | 810 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1]; in radeonInitScreen2() local
820 depth_bits[0] = 0; in radeonInitScreen2()
822 depth_bits[1] = 16; in radeonInitScreen2()
824 depth_bits[2] = 24; in radeonInitScreen2()
826 depth_bits[3] = 24; in radeonInitScreen2()
835 depth_bits, in radeonInitScreen2()
837 ARRAY_SIZE(depth_bits), in radeonInitScreen2()
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| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_screen.c | 810 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1]; in radeonInitScreen2() local
820 depth_bits[0] = 0; in radeonInitScreen2()
822 depth_bits[1] = 16; in radeonInitScreen2()
824 depth_bits[2] = 24; in radeonInitScreen2()
826 depth_bits[3] = 24; in radeonInitScreen2()
835 depth_bits, in radeonInitScreen2()
837 ARRAY_SIZE(depth_bits), in radeonInitScreen2()
|
| /external/mesa3d/src/mesa/drivers/dri/nouveau/ |
| D | nouveau_screen.c | 58 const uint8_t depth_bits[] = { 0, 16, 24, 24 }; in nouveau_get_configs() local
76 depth_bits, stencil_bits, in nouveau_get_configs()
77 ARRAY_SIZE(depth_bits), in nouveau_get_configs()
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| /external/mesa3d/src/mesa/drivers/dri/common/ |
| D | utils.c | 177 const uint8_t * depth_bits, const uint8_t * stencil_bits, in driCreateConfigs() argument
310 (depth_bits[k] || stencil_bits[k])) { in driCreateConfigs()
317 if ((depth_bits[k] + stencil_bits[k] == 16) != in driCreateConfigs()
350 modes->depthBits = depth_bits[k]; in driCreateConfigs()
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| D | utils.h | 44 const uint8_t * depth_bits, const uint8_t * stencil_bits,
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| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| D | intel_screen.c | 1041 uint8_t depth_bits[4], stencil_bits[4]; in intel_screen_make_configs() local
1053 depth_bits[0] = 0; in intel_screen_make_configs()
1057 depth_bits[1] = 16; in intel_screen_make_configs()
1060 depth_bits[1] = 24; in intel_screen_make_configs()
1065 depth_bits, in intel_screen_make_configs()
1081 depth_bits[0] = 16; in intel_screen_make_configs()
1084 depth_bits[0] = 24; in intel_screen_make_configs()
1089 depth_bits, stencil_bits, 1, in intel_screen_make_configs()
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| /external/virglrenderer/src/gallium/auxiliary/util/ |
| D | u_format.c | 212 int depth_bits; in util_get_depth_format_mrd() local
214 depth_bits = desc->channel[depth_channel].size; in util_get_depth_format_mrd()
215 mrd = 1.0 / ((1ULL << depth_bits) - 1); in util_get_depth_format_mrd()
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | intel_screen.c | 2277 uint8_t depth_bits[4], stencil_bits[4]; in intel_screen_make_configs() local
2296 depth_bits[0] = 0; in intel_screen_make_configs()
2301 depth_bits[num_depth_stencil_bits] = 16; in intel_screen_make_configs()
2306 depth_bits[num_depth_stencil_bits] = 24; in intel_screen_make_configs()
2311 depth_bits[num_depth_stencil_bits] = 24; in intel_screen_make_configs()
2317 depth_bits, in intel_screen_make_configs()
2338 depth_bits[0] = 16; in intel_screen_make_configs()
2341 depth_bits[0] = 24; in intel_screen_make_configs()
2344 depth_bits[0] = 0; in intel_screen_make_configs()
2348 depth_bits[0] = 24; in intel_screen_make_configs()
[all …]
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| /external/deqp/external/openglcts/modules/common/ |
| D | glcPolygonOffsetClampTests.cpp | 359 GLint depth_bits = 0; in test() local
360 gl.getIntegerv(GL_DEPTH_BITS, &depth_bits); in test()
361 float num_units = (float)(1 << depth_bits); in test()
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| /external/mesa3d/src/mesa/drivers/dri/swrast/ |
| D | swrast.c | 219 unsigned pixel_bits, unsigned depth_bits, in swrastFillInModes() argument
240 depth_bits_array[2] = depth_bits; in swrastFillInModes()
241 depth_bits_array[3] = depth_bits; in swrastFillInModes()
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| /external/mesa3d/src/util/format/ |
| D | u_format.c | 318 int depth_bits; in util_get_depth_format_mrd() local
320 depth_bits = desc->channel[depth_channel].size; in util_get_depth_format_mrd()
321 mrd = 1.0 / ((1ULL << depth_bits) - 1); in util_get_depth_format_mrd()
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| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_state.c | 246 unsigned depth_bits = in etna_set_framebuffer_state() local
270 cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f); in etna_set_framebuffer_state()
291 ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP); in etna_set_framebuffer_state()
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