Searched refs:ds_add_rtn_u32 (Results 1 – 8 of 8) sorted by relevance
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | atomic_load_add.ll | 24 ; SI: ds_add_rtn_u32
33 ; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:20
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| D | local-atomics.ll | 37 ; GCN: ds_add_rtn_u32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]]
48 ; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
59 ; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
60 ; CIVI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
74 ; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[ONE]]
85 ; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[ONE]] offset:16
96 ; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
97 ; CIVI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
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| D | shl_add_ptr.ll | 149 ; SI: ds_add_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
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| /external/llvm/test/MC/AMDGPU/ |
| D | ds.s | 161 ds_add_rtn_u32 v8, v2, v4 label
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| /external/llvm/test/MC/Disassembler/AMDGPU/ |
| D | ds_vi.txt | 105 # VI: ds_add_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x40,0xd8,0x02,0x04,0x00,0x08]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | DSInstructions.td | 445 defm DS_ADD_RTN_U32 : DS_1A1D_RET_mc<"ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 802 defm DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_instruction_selection.cpp | 6726 op32_rtn = aco_opcode::ds_add_rtn_u32; in visit_shared_atomic()
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