Searched refs:ds_max_rtn_i32 (Results 1 – 7 of 7) sorted by relevance
| /external/llvm/test/MC/AMDGPU/ |
| D | ds.s | 185 ds_max_rtn_i32 v8, v2, v4 label
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | local-atomics.ll | 246 ; GCN: ds_max_rtn_i32
256 ; GCN: ds_max_rtn_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
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| D | shl_add_ptr.ll | 243 ; SI: ds_max_rtn_i32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
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| /external/llvm/test/MC/Disassembler/AMDGPU/ |
| D | ds_vi.txt | 123 # VI: ds_max_rtn_i32 v8, v2, v4 ; encoding: [0x00,0x00,0x4c,0xd8,0x02,0x04,0x00,0x08]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | DSInstructions.td | 452 defm DS_MAX_RTN_I32 : DS_1A1D_RET_mc<"ds_max_rtn_i32", VGPR_32, "ds_max_i32">;
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 808 defm DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "ds_max_rtn_i32", VGPR_32, "ds_max_i32">;
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_instruction_selection.cpp | 6744 op32_rtn = aco_opcode::ds_max_rtn_i32; in visit_shared_atomic()
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