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Searched refs:ds_read2_b64 (Results 1 – 19 of 19) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dload-local-i64.ll19 ; GCN: ds_read2_b64
33 ; GCN-DAG: ds_read2_b64
50 ; GCN: ds_read2_b64
51 ; GCN: ds_read2_b64
70 ; GCN: ds_read2_b64
71 ; GCN: ds_read2_b64
72 ; GCN: ds_read2_b64
73 ; GCN: ds_read2_b64
99 ; GCN: ds_read2_b64
100 ; GCN: ds_read2_b64
[all …]
Dload-local-f64.ll19 ; GCN: ds_read2_b64
33 ; GCN-DAG: ds_read2_b64
50 ; GCN: ds_read2_b64
51 ; GCN: ds_read2_b64
70 ; GCN: ds_read2_b64
71 ; GCN: ds_read2_b64
72 ; GCN: ds_read2_b64
73 ; GCN: ds_read2_b64
99 ; GCN: ds_read2_b64
100 ; GCN: ds_read2_b64
[all …]
Dload-local-f32.ll49 ; GCN: ds_read2_b64
63 ; GCN: ds_read2_b64
64 ; GCN: ds_read2_b64
82 ; GCN: ds_read2_b64
83 ; GCN: ds_read2_b64
84 ; GCN: ds_read2_b64
85 ; GCN: ds_read2_b64
Dload-local-i16.ll54 ; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}}
68 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
69 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}}
223 ; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
232 ; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
242 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1 offset1:2{{$}}
259 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:1{{$}}
269 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
270 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3
271 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5
[all …]
Dload-local-i32.ll39 ; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}}
49 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
50 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}}
59 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:4{{$}}
60 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:5 offset1:6{{$}}
61 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7{{$}}
62 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1 offset1:2{{$}}
Dds_read2_superreg.ll88 ; CI: ds_read2_b64 [[REG_ZW:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}
101 ; CI-DAG: ds_read2_b64 [[REG_ZW:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}
115 ; CI-DAG: ds_read2_b64 [[VEC_HI:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:2 offset1:3{{$}}
116 ; CI-DAG: ds_read2_b64 [[VEC_LO:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}
131 ; CI-DAG: ds_read2_b64 [[VEC0_3:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}
132 ; CI-DAG: ds_read2_b64 [[VEC4_7:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:2 offset1:3{{$}}
133 ; CI-DAG: ds_read2_b64 [[VEC8_11:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:4 offset1:5{{$}}
134 ; CI-DAG: ds_read2_b64 [[VEC12_15:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:6 offset1:7{{$}}
Dindirect-private-64.ll53 ; CI-PROMOTE: ds_read2_b64
111 ; CI-PROMOTE: ds_read2_b64
Dreorder-stores.ll19 ; SI: ds_read2_b64
Dllvm.memcpy.ll156 ; SI: ds_read2_b64
157 ; SI: ds_read2_b64
Dds_read2.ll314 ; SI: ds_read2_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, [[VPTR]] offset1:8
332 ; SI: ds_read2_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:255
348 ; SI-NOT ds_read2_b64
Dds_read2st64.ll240 ; SI: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:8
Dload-local-i8.ll67 ; GCN: ds_read2_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
/external/llvm/test/MC/AMDGPU/
Dds.s449 ds_read2_b64 v[8:11], v2 label
/external/llvm/test/MC/Disassembler/AMDGPU/
Dds_vi.txt321 # VI: ds_read2_b64 v[8:11], v2 ; encoding: [0x00,0x00,0xee,0xd8,0x02,0x00,0x00,0x08]
/external/mesa3d/src/amd/compiler/
Daco_optimizer.cpp1016 … instr->opcode == aco_opcode::ds_write2_b64 || instr->opcode == aco_opcode::ds_read2_b64) { in label_instruction()
1017 …str->opcode == aco_opcode::ds_write2_b64 || instr->opcode == aco_opcode::ds_read2_b64) ? 0x7 : 0x3; in label_instruction()
1018 … (instr->opcode == aco_opcode::ds_write2_b64 || instr->opcode == aco_opcode::ds_read2_b64) ? 3 : 2; in label_instruction()
Daco_instruction_selection.cpp3311 op = aco_opcode::ds_read2_b64; in lds_load_callback()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DDSInstructions.td548 defm DS_READ2_B64 : DS_1A_Off8_RET_mc<"ds_read2_b64", VReg_128>;
/external/mesa3d/docs/relnotes/
D19.3.0.rst2850 - aco: properly combine additions into ds_write2_b64/ds_read2_b64
2851 - aco: use ds_read2_b64/ds_write2_b64
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td889 defm DS_READ2_B64 : DS_1A_Off8_RET <0x77, "ds_read2_b64", VReg_128>;