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/external/vixl/src/aarch64/
Dlogic-aarch64.cc2184 LogicVRegister Simulator::extractnarrow(VectorFormat dstform, in extractnarrow() argument
2190 VectorFormat srcform = dstform; in extractnarrow()
2191 if ((dstform == kFormat16B) || (dstform == kFormat8H) || in extractnarrow()
2192 (dstform == kFormat4S)) { in extractnarrow()
2202 offset = LaneCountFromFormat(dstform) / 2; in extractnarrow()
2205 dst.ClearForWrite(dstform); in extractnarrow()
2213 if (ssrc > MaxIntFromFormat(dstform)) { in extractnarrow()
2215 } else if (ssrc < MinIntFromFormat(dstform)) { in extractnarrow()
2221 if (ssrc > static_cast<int64_t>(MaxUintFromFormat(dstform))) { in extractnarrow()
2227 if (usrc > MaxUintFromFormat(dstform)) { in extractnarrow()
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