| /external/vixl/test/aarch64/ |
| D | test-disasm-sve-aarch64.cc | 224 COMPARE(dupm(z15.VnS(), 0x7f007f00), "dupm z15.h, #0x7f00"); in TEST()
240 COMPARE(dupm(z0.VnH(), 0xfe), "dupm z0.h, #0xfe"); in TEST()
241 COMPARE(dupm(z0.VnH(), 0xff), "dupm z0.h, #0xff"); in TEST()
242 COMPARE(dupm(z0.VnH(), 0x1fe), "mov z0.h, #0x1fe"); in TEST()
243 COMPARE(dupm(z0.VnH(), 0xfe00), "dupm z0.h, #0xfe00"); in TEST()
244 COMPARE(dupm(z0.VnH(), 0xfe01), "mov z0.h, #0xfe01"); in TEST()
245 COMPARE(dupm(z0.VnS(), 0xfe00), "dupm z0.s, #0xfe00"); in TEST()
246 COMPARE(dupm(z0.VnS(), 0xfe000001), "mov z0.s, #0xfe000001"); in TEST()
247 COMPARE(dupm(z0.VnS(), 0xffffff00), "dupm z0.s, #0xffffff00"); in TEST()
248 COMPARE(dupm(z0.VnS(), 0xffffff01), "dupm z0.s, #0xffffff01"); in TEST()
[all …]
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| D | test-assembler-sve-aarch64.cc | 1387 __ dupm(z13.VnD(), 0x7ffffff800000000); in TEST_SVE() local
1388 __ dupm(z14.VnS(), 0x7ffc7ffc); in TEST_SVE() local
1389 __ dupm(z15.VnH(), 0x3ffc); in TEST_SVE() local
1390 __ dupm(z16.VnB(), 0xc3); in TEST_SVE() local
|
| /external/vixl/src/aarch64/ |
| D | macro-assembler-sve-aarch64.cc | 490 dupm(zd, imm.AsUintN(lane_size)); in Dup()
|
| D | assembler-sve-aarch64.cc | 107 void Assembler::dupm(const ZRegister& zd, uint64_t imm) { in dupm() function in vixl::aarch64::Assembler
6586 dupm(zd, imm); in mov()
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| D | assembler-aarch64.h | 4034 void dupm(const ZRegister& zd, uint64_t imm);
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | SVEInstrFormats.td | 1322 def : InstAlias<"dupm $Zd, $imm",
1324 def : InstAlias<"dupm $Zd, $imm",
1326 def : InstAlias<"dupm $Zd, $imm",
|
| D | AArch64SVEInstrInfo.td | 248 defm DUPM_ZI : sve_int_dup_mask_imm<"dupm">;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12494 "decp\004decw\003dmb\004drps\003dsb\003dup\004dupm\003eon\003eor\004eor3"
13538 …{ 966 /* dupm */, AArch64::DUPM_ZI, Convert__SVEVectorHReg1_0__SVELogicalImm161_1, AMFBS_HasSVE, {…
13539 …{ 966 /* dupm */, AArch64::DUPM_ZI, Convert__SVEVectorSReg1_0__SVELogicalImm321_1, AMFBS_HasSVE, {…
13540 …{ 966 /* dupm */, AArch64::DUPM_ZI, Convert__SVEVectorDReg1_0__LogicalImm641_1, AMFBS_HasSVE, { MC…
13541 …{ 966 /* dupm */, AArch64::DUPM_ZI, Convert__SVEVectorBReg1_0__SVELogicalImm81_1, AMFBS_HasSVE, { …
20911 …{ 966 /* dupm */, AArch64::DUPM_ZI, Convert__SVEVectorHReg1_0__SVELogicalImm161_1, AMFBS_HasSVE, {…
20912 …{ 966 /* dupm */, AArch64::DUPM_ZI, Convert__SVEVectorSReg1_0__SVELogicalImm321_1, AMFBS_HasSVE, {…
20913 …{ 966 /* dupm */, AArch64::DUPM_ZI, Convert__SVEVectorDReg1_0__LogicalImm641_1, AMFBS_HasSVE, { MC…
20914 …{ 966 /* dupm */, AArch64::DUPM_ZI, Convert__SVEVectorBReg1_0__SVELogicalImm81_1, AMFBS_HasSVE, { …
29381 { 966 /* dupm */, 1 /* 0 */, MCK_SVEVectorHReg, AMFBS_HasSVE },
[all …]
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| D | AArch64GenAsmWriter.inc | 22178 /* 1055 */ "dupm $\xFF\x01\x06, $\xFF\x02\x08\0"
22179 /* 1071 */ "dupm $\xFF\x01\x09, $\xFF\x02\x0A\0"
22180 /* 1087 */ "dupm $\xFF\x01\x0B, $\xFF\x02\x04\0"
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| D | AArch64GenAsmWriter1.inc | 22899 /* 1055 */ "dupm $\xFF\x01\x06, $\xFF\x02\x08\0"
22900 /* 1071 */ "dupm $\xFF\x01\x09, $\xFF\x02\x0A\0"
22901 /* 1087 */ "dupm $\xFF\x01\x0B, $\xFF\x02\x04\0"
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 7244 void dupm(const ZRegister& zd, uint64_t imm)
|