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Searched refs:f32x4 (Results 1 – 25 of 26) sorted by relevance

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/external/rust/crates/glam/src/
Dcoresimd.rs5 pub(crate) fn dot3_in_x(lhs: f32x4, rhs: f32x4) -> f32x4 { in dot3_in_x() argument
15 pub(crate) fn dot4_in_x(lhs: f32x4, rhs: f32x4) -> f32x4 { in dot4_in_x() argument
24 pub(crate) fn dot3(lhs: f32x4, rhs: f32x4) -> f32 { in dot3() argument
29 pub(crate) fn dot3_into_f32x4(lhs: f32x4, rhs: f32x4) -> f32x4 { in dot3_into_f32x4() argument
35 pub(crate) fn dot4(lhs: f32x4, rhs: f32x4) -> f32 { in dot4() argument
40 pub(crate) fn dot4_into_f32x4(lhs: f32x4, rhs: f32x4) -> f32x4 { in dot4_into_f32x4() argument
46 pub(crate) fn f32x4_bitand(a: f32x4, b: f32x4) -> f32x4 { in f32x4_bitand() argument
49 f32x4::from_bits(a & b) in f32x4_bitand()
53 pub(crate) fn f32x4_bitxor(a: f32x4, b: f32x4) -> f32x4 { in f32x4_bitxor() argument
56 f32x4::from_bits(a ^ b) in f32x4_bitxor()
Dsse2.rs8 f32x4: [f32; 4],
12 pub const fn m128_from_f32x4(f32x4: [f32; 4]) -> __m128 { in m128_from_f32x4()
13 unsafe { UnionCast { f32x4 }.m128 }
Dwasm32.rs4 f32x4(a[0], a[1], a[2], a[3])
/external/rust/crates/glam/src/f32/coresimd/
Dvec4.rs28 pub struct Vec4(pub(crate) f32x4);
73 Self(f32x4::from_array([x, y, z, w])) in new()
202 BVec4A(f32x4::simd_eq(self.0, rhs.0)) in cmpeq()
212 BVec4A(f32x4::simd_ne(self.0, rhs.0)) in cmpne()
222 BVec4A(f32x4::simd_ge(self.0, rhs.0)) in cmpge()
232 BVec4A(f32x4::simd_gt(self.0, rhs.0)) in cmpgt()
242 BVec4A(f32x4::simd_le(self.0, rhs.0)) in cmple()
252 BVec4A(f32x4::simd_lt(self.0, rhs.0)) in cmplt()
290 f32x4::is_finite(self.0).all() in is_finite()
304 BVec4A(f32x4::is_nan(self.0)) in is_nan_mask()
[all …]
Dvec3a.rs31 pub struct Vec3A(pub(crate) f32x4);
70 Self(f32x4::from_array([x, y, z, z])) in new()
226 BVec3A(f32x4::simd_eq(self.0, rhs.0)) in cmpeq()
236 BVec3A(f32x4::simd_ne(self.0, rhs.0)) in cmpne()
246 BVec3A(f32x4::simd_ge(self.0, rhs.0)) in cmpge()
256 BVec3A(f32x4::simd_gt(self.0, rhs.0)) in cmpgt()
266 BVec3A(f32x4::simd_le(self.0, rhs.0)) in cmple()
276 BVec3A(f32x4::simd_lt(self.0, rhs.0)) in cmplt()
314 f32x4::is_finite(self.0) in is_finite()
330 BVec3A(f32x4::is_nan(self.0)) in is_nan_mask()
[all …]
Dquat.rs38 pub struct Quat(pub(crate) f32x4);
63 Self(f32x4::from_array([x, y, z, w])) in from_xyzw()
74 Self(f32x4::from_array(a))
392 const SIGN: f32x4 = f32x4::from_array([-1.0, -1.0, -1.0, 1.0]); in conjugate()
541 const NEG_ZERO: f32x4 = f32x4::from_array([-0.0; 4]); in lerp()
548 let interpolated = start + ((f32x4_bitxor(end, bias) - start) * f32x4::splat(s)); in lerp()
591 let tmp = f32x4::from_array([x, y, z, w]); in slerp()
629 const CONTROL_WZYX: f32x4 = f32x4::from_array([1.0, -1.0, 1.0, -1.0]); in mul_quat()
630 const CONTROL_ZWXY: f32x4 = f32x4::from_array([1.0, 1.0, -1.0, -1.0]); in mul_quat()
631 const CONTROL_YXWZ: f32x4 = f32x4::from_array([-1.0, 1.0, 1.0, -1.0]); in mul_quat()
[all …]
Dmat2.rs24 pub struct Mat2(pub(crate) f32x4);
39 Self(f32x4::from_array([m00, m01, m10, m11])) in new()
45 Self(f32x4::from_array([x_axis.x, x_axis.y, y_axis.x, y_axis.y])) in from_cols()
53 Self(f32x4::from_array(*m))
217 const SIGN: f32x4 = f32x4::from_array([1.0, -1.0, -1.0, 1.0]); in inverse()
233 let xxyy = f32x4::from_array([rhs.x, rhs.x, rhs.y, rhs.y]); in mul_vec2()
237 unsafe { *(&result as *const f32x4 as *const Vec2) } in mul_vec2() constant
274 Self(self.0 * f32x4::splat(rhs)) in mul_scalar()
Dmat4.rs626 let detcof = addres * f32x4::from_array([1.0, -1.0, 1.0, -1.0]); in determinant()
815 let sign_a = f32x4::from_array([-1.0, 1.0, -1.0, 1.0]); in inverse()
816 let sign_b = f32x4::from_array([1.0, -1.0, 1.0, -1.0]); in inverse()
881 let rcp0 = f32x4::splat(dot0.recip()); in inverse()
/external/rust/crates/rand/src/distributions/
Dfloat.rs159 float_impls! { f32x4, u32x4, f32, u32, 23, 127 }
215 test_f32! { f32x4_edge_cases, f32x4, f32x4::splat(0.0), f32x4::splat(EPSILON32) }
Dutils.rs424 #[cfg(feature="simd_support")] simd_impl! { f32x4, f32, m32x4, u32x4 }
Duniform.rs1004 uniform_float_impl! { f32x4, u32x4, f32, u32, 32 - 23 }
1421 t!(f32x4, f32, 32 - 23); in test_floats()
1495 t!(f32x4, f32); in test_float_assertions()
/external/skia/modules/canvaskit/wasm_tools/SIMD/
Dwasm_simd_types.txt10 f32x4
/external/rust/crates/glam/src/f32/wasm32/
Dmat2.rs39 Self(f32x4(m00, m01, m10, m11)) in new()
45 Self(f32x4(x_axis.x, x_axis.y, y_axis.x, y_axis.y)) in from_cols()
234 let xxyy = f32x4(rhs.x, rhs.x, rhs.y, rhs.y); in mul_vec2()
Dquat.rs63 Self(f32x4(x, y, z, w)) in from_xyzw()
601 let tmp = f32x4(x, y, z, w); in slerp()
Dmat4.rs594 let detcof = f32x4_mul(addres, f32x4(1.0, -1.0, 1.0, -1.0)); in determinant()
687 let sign_a = f32x4(-1.0, 1.0, -1.0, 1.0); in inverse()
688 let sign_b = f32x4(1.0, -1.0, 1.0, -1.0); in inverse()
Dvec4.rs77 Self(f32x4(x, y, z, w)) in new()
Dvec3a.rs74 Self(f32x4(x, y, z, z)) in new()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrSIMD.td312 defm "" : Splat<v4f32, "f32x4", F32, splat4, 18>;
378 defm "" : ExtractLane<v4f32, "f32x4", LaneIdx4, F32, 19>;
427 defm "" : ReplaceLane<v4f32, "f32x4", LaneIdx4, F32, f32, 20>;
467 defm "" : SIMDCondition<v4f32, v4i32, "f32x4", name, cond, baseInst>;
773 defm "" : SIMDUnary<v4f32, "f32x4", node, name, baseInst>;
792 defm "" : SIMDBinary<v4f32, "f32x4", node, name, baseInst>;
830 defm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_i32x4_s", 175>;
831 defm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_i32x4_u", 176>;
917 defm "" : SIMDQFM<v4f32, "f32x4", 0x98>;
/external/neon_2_sse/
DNEON_2_SSE.h15768 float32x4x2_t f32x4; in vtrnq_f32() local
15773 f32x4.val[0] = _mm_unpacklo_ps(a_sh, b_sh); //a0, b0, a2, b2 in vtrnq_f32()
15774 f32x4.val[1] = _mm_unpackhi_ps(a_sh, b_sh); //a1, b1, a3, b3 in vtrnq_f32()
15775 return f32x4; in vtrnq_f32()
15867 float32x4x2_t f32x4; in vzipq_f32() local
15868 f32x4.val[0] = _mm_unpacklo_ps ( a, b); in vzipq_f32()
15869 f32x4.val[1] = _mm_unpackhi_ps ( a, b); in vzipq_f32()
15870 return f32x4; in vzipq_f32()
/external/llvm/test/CodeGen/X86/
Davx512-intrinsics.ll4851 declare <16 x float> @llvm.x86.avx512.mask.shuf.f32x4(<16 x float>, <16 x float>, i32, <16 x float>…
4861 …%res = call <16 x float> @llvm.x86.avx512.mask.shuf.f32x4(<16 x float> %x0, <16 x float> %x1, i32 …
4862 …%res1 = call <16 x float> @llvm.x86.avx512.mask.shuf.f32x4(<16 x float> %x0, <16 x float> %x1, i32…
Davx512vl-intrinsics.ll4374 declare <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float>, <8 x float>, i32, <8 x float>…
4389 …%res = call <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float> %x0, <8 x float> %x1, i32…
4390 …%res1 = call <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float> %x0, <8 x float> %x1, i3…
4391 …%res2 = call <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float> %x0, <8 x float> %x1, i3…
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen5216 x86_avx512_mask_shuf_f32x4, // llvm.x86.avx512.mask.shuf.f32x4
5217 x86_avx512_mask_shuf_f32x4_256, // llvm.x86.avx512.mask.shuf.f32x4.256
11274 "llvm.x86.avx512.mask.shuf.f32x4",
11275 "llvm.x86.avx512.mask.shuf.f32x4.256",
19214 1, // llvm.x86.avx512.mask.shuf.f32x4
19215 1, // llvm.x86.avx512.mask.shuf.f32x4.256
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen5216 x86_avx512_mask_shuf_f32x4, // llvm.x86.avx512.mask.shuf.f32x4
5217 x86_avx512_mask_shuf_f32x4_256, // llvm.x86.avx512.mask.shuf.f32x4.256
11274 "llvm.x86.avx512.mask.shuf.f32x4",
11275 "llvm.x86.avx512.mask.shuf.f32x4.256",
19214 1, // llvm.x86.avx512.mask.shuf.f32x4
19215 1, // llvm.x86.avx512.mask.shuf.f32x4.256
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen5216 x86_avx512_mask_shuf_f32x4, // llvm.x86.avx512.mask.shuf.f32x4
5217 x86_avx512_mask_shuf_f32x4_256, // llvm.x86.avx512.mask.shuf.f32x4.256
11274 "llvm.x86.avx512.mask.shuf.f32x4",
11275 "llvm.x86.avx512.mask.shuf.f32x4.256",
19214 1, // llvm.x86.avx512.mask.shuf.f32x4
19215 1, // llvm.x86.avx512.mask.shuf.f32x4.256
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen5192 x86_avx512_mask_shuf_f32x4, // llvm.x86.avx512.mask.shuf.f32x4
5193 x86_avx512_mask_shuf_f32x4_256, // llvm.x86.avx512.mask.shuf.f32x4.256
11216 "llvm.x86.avx512.mask.shuf.f32x4",
11217 "llvm.x86.avx512.mask.shuf.f32x4.256",
19101 1, // llvm.x86.avx512.mask.shuf.f32x4
19102 1, // llvm.x86.avx512.mask.shuf.f32x4.256

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