| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vcvt_f.ll | 51 ; CHECK: fcvtxn2
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| D | arm64-vcvt.ll | 535 ;CHECK: fcvtxn2 v0.4s, v1.2d
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| /external/capstone/suite/MC/AArch64/ |
| D | neon-simd-misc.s.cs | 138 0x06,0x69,0x61,0x6e = fcvtxn2 v6.4s, v8.2d
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| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-misc.s | 437 fcvtxn2 v6.4s, v8.2d
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| D | arm64-advsimd.s | 867 fcvtxn2 v7.4s, v8.2d
874 ; CHECK: fcvtxn2 v7.4s, v8.2d ; encoding: [0x07,0x69,0x61,0x6e]
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| D | neon-diagnostics.s | 5821 fcvtxn2 v4.2s, v0.2d
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| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 4308 LogicVRegister fcvtxn2(VectorFormat vform,
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| D | assembler-aarch64.h | 2384 void fcvtxn2(const VRegister& vd, const VRegister& vn);
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| D | assembler-aarch64.cc | 3089 void Assembler::fcvtxn2(const VRegister& vd, const VRegister& vn) { in fcvtxn2() function in vixl::aarch64::Assembler
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| D | logic-aarch64.cc | 6052 LogicVRegister Simulator::fcvtxn2(VectorFormat vform, in fcvtxn2() function in vixl::aarch64::Simulator
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| D | macro-assembler-aarch64.h | 1481 fcvtxn2(vd, vn); in Fcvtxn2()
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| D | simulator-aarch64.cc | 6812 fcvtxn2(vf_fcvtn, rd, rn); in VisitNEON2RegMisc()
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 564 # CHECK: fcvtxn2 v0.4s, v0.2d
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 2598 __ fcvtxn2(v31.V4S(), v25.V2D()); in GenerateTestSequenceNEONFP() local
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| D | test-cpu-features-aarch64.cc | 3221 TEST_FP_NEON(fcvtxn2_0, fcvtxn2(v0.V4S(), v1.V2D()))
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm-colour | 2244 0x~~~~~~~~~~~~~~~~ 6e616b3f fcvtxn2 v31.4s, v25.2d
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| D | log-disasm | 2244 0x~~~~~~~~~~~~~~~~ 6e616b3f fcvtxn2 v31.4s, v25.2d
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| D | log-cpufeatures-custom | 2243 0x~~~~~~~~~~~~~~~~ 6e616b3f fcvtxn2 v31.4s, v25.2d ### {FP, NEON} ###
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| D | log-cpufeatures | 2243 0x~~~~~~~~~~~~~~~~ 6e616b3f fcvtxn2 v31.4s, v25.2d // Needs: FP, NEON
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| D | log-cpufeatures-colour | 2243 0x~~~~~~~~~~~~~~~~ 6e616b3f fcvtxn2 v31.4s, v25.2d [1;35mFP, NEON[0;m
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| D | log-all | 9742 0x~~~~~~~~~~~~~~~~ 6e616b3f fcvtxn2 v31.4s, v25.2d
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| /external/capstone/arch/AArch64/ |
| D | AArch64MappingInsnOp.inc | 1757 { /* AArch64_FCVTXNv4f32, ARM64_INS_FCVTXN2: fcvtxn2 $rd.4s, $rn.2d */
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 3812 void fcvtxn2(const VRegister& vd, const VRegister& vn)
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12501 "tnu\006fcvtps\006fcvtpu\005fcvtx\006fcvtxn\007fcvtxn2\007fcvtxnt\006fcv"
14065 …{ 1298 /* fcvtxn2 */, AArch64::FCVTXNv4f32, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2, A…
21438 …{ 1298 /* fcvtxn2 */, AArch64::FCVTXNv4f32, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2, A…
|