| /external/llvm/test/MC/Disassembler/X86/ |
| D | fp-stack.txt | 172 # CHECK: fdivr %st(0)
175 # CHECK: fdivr %st(1)
178 # CHECK: fdivr %st(2)
181 # CHECK: fdivr %st(3)
184 # CHECK: fdivr %st(4)
187 # CHECK: fdivr %st(5)
190 # CHECK: fdivr %st(6)
193 # CHECK: fdivr %st(7)
697 # CHECK: fdivr %st(0), %st(0)
700 # CHECK: fdivr %st(0), %st(1)
[all …]
|
| D | x86-16.txt | 198 # CHECK: fdivr %st(0)
|
| /external/llvm/test/MC/X86/ |
| D | intel-syntax-2.s | 30 fdivr label
|
| D | intel-syntax.s | 552 fdivr label
578 fdivr ST(0), ST(1) label
591 fdivr ST(1), ST(0) label
604 fdivr ST(1) label
|
| D | x86-64.s | 1438 fdivr %st(1), %st(0) label
1451 fdivr %st(0), %st(1) label
1464 fdivr %st(1) label
|
| D | x86-16.s | 237 fdivr %st(0), %st
|
| D | x86-32.s | 343 fdivr %st(0), %st
|
| D | x86-32-coverage.s | 2577 fdivr %st(2)
|
| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 717 #define FDIVR2(a, b) CHOICE(fdivr ARG2(a,b), fdivr ARG2(a,b), fdivr ARG2(b,a))
1428 #define FDIVR_D(a) fdivr D_(a)
1429 #define FDIVR_S(a) fdivr S_(a)
1430 #define FDIVR2(a, b) fdivr b, a
|
| /external/elfutils/libcpu/defs/ |
| D | i386 | 312 11011000,11111{freg}:fdivr {freg},%st
313 11011100,11111{freg}:fdivr %st,{freg}
314 11011{D}00,{mod}111{r_m}:fdivr{D} {mod}{r_m}
|
| /external/elfutils/tests/ |
| D | testfile44.expect.bz2 | 1testfile44.o: elf32-elf_i386
2
3Disassembly of section .text:
4
5 0 ... |
| D | testfile45.expect.bz2 | 1testfile45.o: elf64-elf_x86_64
2
3Disassembly of section .text:
4
5 0 ... |
| /external/llvm/lib/Target/X86/ |
| D | X86InstrFPStack.td | 284 def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t$op">;
|
| D | X86InstrInfo.td | 2877 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrFPStack.td | 343 def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t{$op, %st|st, $op}">;
|
| D | X86InstrInfo.td | 3359 defm : FpUnaryAlias<"fdivr", DIVR_FST0r, 0>;
|
| /external/vixl/test/aarch64/ |
| D | test-api-movprfx-aarch64.cc | 427 __ fdivr(z12.VnD(), p7.Merging(), z12.VnD(), z12.VnD()); in TEST() local
943 __ fdivr(z7.VnH(), p7.Merging(), z7.VnH(), z28.VnH()); in TEST() local
1787 __ fdivr(z6.VnD(), p1.Merging(), z6.VnD(), z5.VnD()); in TEST() local
|
| D | test-disasm-sve-aarch64.cc | 889 COMPARE(fdivr(z21.VnH(), p3.Merging(), z21.VnH(), z11.VnH()), in TEST()
891 COMPARE(fdivr(z23.VnS(), p5.Merging(), z23.VnS(), z15.VnS()), in TEST()
893 COMPARE(fdivr(z25.VnD(), p7.Merging(), z25.VnD(), z19.VnD()), in TEST()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SVEInstrInfo.td | 204 defm FDIVR_ZPmZ : sve_fp_2op_p_zds<0b1100, "fdivr", int_aarch64_sve_fdivr>;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12502 "tzs\006fcvtzu\004fdiv\005fdivr\004fdup\005fexpa\007fjcvtzs\005flogb\004"
14148 …{ 1333 /* fdivr */, AArch64::FDIVR_ZPmZ_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie…
14149 …{ 1333 /* fdivr */, AArch64::FDIVR_ZPmZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie…
14150 …{ 1333 /* fdivr */, AArch64::FDIVR_ZPmZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie…
21521 …{ 1333 /* fdivr */, AArch64::FDIVR_ZPmZ_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie…
21522 …{ 1333 /* fdivr */, AArch64::FDIVR_ZPmZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie…
21523 …{ 1333 /* fdivr */, AArch64::FDIVR_ZPmZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie…
30091 { 1333 /* fdivr */, 2 /* 1 */, MCK_SVEPredicate3bAnyReg, AMFBS_HasSVE },
30092 { 1333 /* fdivr */, 49 /* 0, 4, 5 */, MCK_SVEVectorHReg, AMFBS_HasSVE },
30093 { 1333 /* fdivr */, 2 /* 1 */, MCK_SVEPredicate3bAnyReg, AMFBS_HasSVE },
[all …]
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 4231 void fdivr(const ZRegister& zd,
|
| D | assembler-sve-aarch64.cc | 640 void Assembler::fdivr(const ZRegister& zd, in fdivr() function in vixl::aarch64::Assembler
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenAsmMatcher.inc | 7656 "omps\005fcoms\004fcos\007fdecstp\004fdiv\005fdivl\005fdivp\005fdivr\006"
8670 { 2281 /* fdivr */, X86::DIVR_FST0r, Convert__Reg1_0, AMFBS_None, { MCK_RST }, },
8671 { 2281 /* fdivr */, X86::DIVR_FST0r, Convert__regST0, AMFBS_None, { MCK_ST0, MCK_ST0 }, },
8672 { 2281 /* fdivr */, X86::DIV_FrST0, Convert__Reg1_1, AMFBS_None, { MCK_ST0, MCK_RST }, },
8673 { 2281 /* fdivr */, X86::DIVR_FST0r, Convert__Reg1_0, AMFBS_None, { MCK_RST, MCK_ST0 }, },
23243 { 2281 /* fdivr */, X86::DIVR_FST0r, Convert__Reg1_0, AMFBS_None, { MCK_RST }, },
23244 { 2281 /* fdivr */, X86::DIVR_F32m, Convert__Mem325_0, AMFBS_None, { MCK_Mem32 }, },
23245 { 2281 /* fdivr */, X86::DIVR_F64m, Convert__Mem645_0, AMFBS_None, { MCK_Mem64 }, },
23246 { 2281 /* fdivr */, X86::DIVR_FST0r, Convert__regST0, AMFBS_None, { MCK_ST0, MCK_ST0 }, },
23247 { 2281 /* fdivr */, X86::DIVR_FST0r, Convert__Reg1_1, AMFBS_None, { MCK_ST0, MCK_RST }, },
[all …]
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 7654 void fdivr(const ZRegister& zd,
|
| /external/capstone/arch/X86/ |
| D | X86MappingInsnOp.inc | 2320 { /* X86_DIVR_F32m, X86_INS_FDIVR: fdivr{s} $src */
2324 { /* X86_DIVR_F64m, X86_INS_FDIVR: fdivr{l} $src */
2340 { /* X86_DIVR_FST0r, X86_INS_FDIVR: fdivr $op */
|