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Searched refs:flat_load_dword (Results 1 – 24 of 24) sorted by relevance

/external/llvm/test/MC/AMDGPU/
Dflat.s18 flat_load_dword v1, v[3:4] label
23 flat_load_dword v1, v[3:4] glc label
28 flat_load_dword v1, v[3:4] glc slc label
33 flat_load_dword v1, v[3:4] glc tfe label
38 flat_load_dword v1, v[3:4] glc slc tfe label
43 flat_load_dword v1, v[3:4] slc label
48 flat_load_dword v1, v[3:4] slc tfe label
53 flat_load_dword v1, v[3:4] tfe label
154 flat_load_dword v1, v[3:4] label
Dreg-syntax-extra.s93 flat_load_dword v[8:8], v[2:3] label
96 flat_load_dword v[63/8+1:65/8], v[2:3] label
99 flat_load_dword v8, v[2*2-2:(3+7)/3] label
102 flat_load_dword v[63/8+1], v[2:3] label
Dmacro-examples.s11 flat_load_dword v[8 + \iter], v[2:3]
/external/llvm/test/CodeGen/AMDGPU/
Dglobal-variable-relocs.ll21 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
35 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
52 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
69 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
86 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
103 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
120 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
137 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
154 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
171 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
[all …]
Dwaitcnt-flat.ll4 ; If flat_store_dword and flat_load_dword use different registers for the data
11 ; XGCN: flat_load_dword [[DATA]], v[{{[0-9]+:[0-9]+}}]
Dinline-constraints.ll5 ; GCN: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
15 %v32 = tail call i32 asm sideeffect "flat_load_dword $0, $1", "=v,v"(i32 addrspace(1)* %ptr)
Dload-global-i32.ll9 ; GCN-HSA: flat_load_dword
94 ; GCN-HSA-DAG: flat_load_dword v[[LO:[0-9]+]],
110 ; GCN-HSA: flat_load_dword v[[LO:[0-9]+]]
131 ; GCN-HSA: flat_load_dword
142 ; GCN-HSA: flat_load_dword v[[LO:[0-9]+]]
Dload-weird-sizes.ll22 ; CI-HSA: flat_load_dword [[VAL:v[0-9]+]]
Dsalu-to-valu.ll95 ; GCN-HSA: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
114 ; GCN-HSA: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
248 ; GCN-HSA: flat_load_dword [[MOVED:v[0-9]+]], v[{{[0-9+:[0-9]+}}]
265 ; GCN-HSA flat_load_dword v{{[0-9]}}, v{{[0-9]+:[0-9]+}}
279 ; GCN-HSA: flat_load_dword v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}]
Dload-global-i8.ll34 ; GCN-HSA: flat_load_dword v
46 ; GCN-HSA: flat_load_dword v
155 ; GCN-HSA: flat_load_dword v
170 ; GCN-HSA: flat_load_dword v
185 ; GCN-HSA: flat_load_dword
200 ; GCN-HSA: flat_load_dword
Dload-global-f32.ll10 ; GCN-HSA: flat_load_dword
Daddrspacecast.ll69 ; HSA: flat_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}
234 ; HSA: flat_load_dword
Dcgp-addressing-modes-flat.ll12 ; GCN: flat_load_dword
Dload-global-i16.ll23 ; GCN-HSA: flat_load_dword v
140 ; GCN-HSA: flat_load_dword
151 ; GCN-HSA: flat_load_dword
Dsra.ll217 ; VI: flat_load_dword v[[HI:[0-9]+]]
244 ; VI: flat_load_dword v[[HI:[0-9]+]]
Dflat-address-space.ll64 ; CHECK: flat_load_dword
Dflat_atomics.ll891 ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
902 ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc
912 ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}}
924 ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}}
Dglobal_atomics.ll960 ; VI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
972 ; VI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc
983 ; VI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}}
996 ; VI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}}
Dcgp-addressing-modes.ll199 ; VI: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dflat_vi.txt3 # VI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x00,0x01]
6 # VI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x00,0x01]
9 # VI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
12 # VI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x80,0x01]
15 # VI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x80,0x01]
18 # VI: flat_load_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x52,0xdc,0x03,0x00,0x00,0x01]
21 # VI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x52,0xdc,0x03,0x00,0x80,0x01]
24 # VI: flat_load_dword v1, v[3:4] tfe ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x80,0x01]
57 # VI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x00,0x01]
/external/llvm/test/Object/AMDGPU/
Dobjdump.s39 flat_load_dword v0, v[10:11]
/external/llvm/lib/Target/AMDGPU/
DCIInstructions.td126 flat<0xc, 0x14>, "flat_load_dword", VGPR_32
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DFLATInstructions.td383 def FLAT_LOAD_DWORD : FLAT_Load_Pseudo <"flat_load_dword", VGPR_32>;
/external/mesa3d/src/amd/compiler/
Daco_instruction_selection.cpp3486 …o_opcode::buffer_load_dword : global ? aco_opcode::global_load_dword : aco_opcode::flat_load_dword; in global_load_callback()