| /external/vixl/src/aarch64/ |
| D | macro-assembler-sve-aarch64.cc | 1825 V(Fmlalt, fmlalt, FourRegDestructiveHelper) \
1857 V(Fmlalt, fmlalt, FourRegOneImmDestructiveHelper) \
|
| D | assembler-aarch64.h | 6026 void fmlalt(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm);
6048 void fmlalt(const ZRegister& zda,
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| D | assembler-sve-aarch64.cc | 7145 void Assembler::fmlalt(const ZRegister& zda, in fmlalt() function in vixl::aarch64::Assembler
7159 void Assembler::fmlalt(const ZRegister& zda, in fmlalt() function in vixl::aarch64::Assembler
|
| /external/vixl/test/aarch64/ |
| D | test-api-movprfx-aarch64.cc | 2043 __ fmlalt(z18.VnS(), z13.VnH(), z5.VnH()); in TEST() local
2046 __ fmlalt(z18.VnS(), z13.VnH(), z5.VnH(), 0); in TEST() local
2898 __ fmlalt(z18.VnS(), z13.VnH(), z5.VnH()); in TEST() local
2901 __ fmlalt(z18.VnS(), z13.VnH(), z5.VnH(), 0); in TEST() local
3230 __ fmlalt(z18.VnS(), z13.VnH(), z18.VnH()); in TEST() local
3233 __ fmlalt(z18.VnS(), z18.VnH(), z5.VnH(), 0); in TEST() local
|
| D | test-disasm-sve-aarch64.cc | 8376 COMPARE(fmlalt(z18.VnS(), z13.VnH(), z5.VnH()), "fmlalt z18.s, z13.h, z5.h"); in TEST()
8377 COMPARE(fmlalt(z18.VnS(), z7.VnH(), z16.VnH()), "fmlalt z18.s, z7.h, z16.h"); in TEST()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SVEInstrInfo.td | 1534 …defm FMLALT_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b01, "fmlalt", int_aarch64_sve_fmlalt_lan…
1540 defm FMLALT_ZZZ_SHH : sve2_fp_mla_long<0b01, "fmlalt", int_aarch64_sve_fmlalt>;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12505 "mlal\006fmlal2\006fmlalb\006fmlalt\004fmls\005fmlsl\006fmlsl2\006fmlslb"
14320 …{ 1480 /* fmlalt */, AArch64::FMLALT_ZZZ_SHH, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_…
14321 …{ 1480 /* fmlalt */, AArch64::FMLALT_ZZZI_SHH, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1…
21693 …{ 1480 /* fmlalt */, AArch64::FMLALT_ZZZ_SHH, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_…
21694 …{ 1480 /* fmlalt */, AArch64::FMLALT_ZZZI_SHH, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1…
30395 { 1480 /* fmlalt */, 6 /* 1, 2 */, MCK_SVEVectorHReg, AMFBS_HasSVE2 },
30396 { 1480 /* fmlalt */, 1 /* 0 */, MCK_SVEVectorSReg, AMFBS_HasSVE2 },
30397 { 1480 /* fmlalt */, 6 /* 1, 2 */, MCK_SVEVectorHReg, AMFBS_HasSVE2 },
30398 { 1480 /* fmlalt */, 1 /* 0 */, MCK_SVEVectorSReg, AMFBS_HasSVE2 },
30399 { 1480 /* fmlalt */, 2 /* 1 */, MCK_SVEVectorHReg, AMFBS_HasSVE2 },
[all …]
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 7887 void fmlalt(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm)
7894 void fmlalt(const ZRegister& zda,
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/ |
| D | IntrinsicImpl.inc | 623 "llvm.aarch64.sve.fmlalt",
624 "llvm.aarch64.sve.fmlalt.lane",
10756 1, // llvm.aarch64.sve.fmlalt
10757 1, // llvm.aarch64.sve.fmlalt.lane
|