| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 334 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
342 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
358 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
366 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
374 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
382 return MI.getDesc().TSFlags & SIInstrFlags::SOPK; in isSOPK()
390 return MI.getDesc().TSFlags & SIInstrFlags::SOPP; in isSOPP()
398 return MI.getDesc().TSFlags & SIInstrFlags::IsPacked; in isPacked()
406 return MI.getDesc().TSFlags & SIInstrFlags::VOP1; in isVOP1()
414 return MI.getDesc().TSFlags & SIInstrFlags::VOP2; in isVOP2()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 184 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
192 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
208 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
216 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
224 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
232 return MI.getDesc().TSFlags & SIInstrFlags::SOPK; in isSOPK()
240 return MI.getDesc().TSFlags & SIInstrFlags::SOPP; in isSOPP()
248 return MI.getDesc().TSFlags & SIInstrFlags::VOP1; in isVOP1()
256 return MI.getDesc().TSFlags & SIInstrFlags::VOP2; in isVOP2()
264 return MI.getDesc().TSFlags & SIInstrFlags::VOP3; in isVOP3()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonShuffler.cpp | 155 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); in HexagonCVIResource()
156 setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore()); in HexagonCVIResource()
229 MCInst const &Inst = ISJ->getDesc(); in restrictSlot1AOK()
237 MCInst const &Inst = ISJ->getDesc(); in restrictSlot1AOK()
260 MCInst const &Inst = ISJ->getDesc(); in restrictNoSlot1Store()
269 MCInst const &Inst = ISJ->getDesc(); in restrictNoSlot1Store()
270 if (HexagonMCInstrInfo::getDesc(MCII, Inst).mayStore()) { in restrictNoSlot1Store()
315 MCInst const &ID = ISJ->getDesc(); in check()
347 if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn()) in check()
379 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { in check()
[all …]
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| D | HexagonMCInstrInfo.cpp | 211 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMemAccessSize()
218 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAddrMode()
223 MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII, in getDesc() function in HexagonMCInstrInfo
286 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
304 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
310 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
316 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtentSigned()
349 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp()
374 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp2()
402 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getUnits()
[all …]
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| D | HexagonMCChecker.cpp | 87 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init()
302 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in reportBranchErrors()
313 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in checkHWLoop()
327 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in checkCOFMax1()
415 bool Branch = HexagonMCInstrInfo::getDesc(MCII, I).isBranch(); in checkNewValues()
455 HexagonMCInstrInfo::getDesc(MCII, *std::get<0>(Producer)); in checkNewValues()
496 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs(); in checkRegistersReadOnly()
513 for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(), in registerUsed()
529 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in registerProducer()
554 HexagonMCInstrInfo::getDesc(MCII, I).mayLoad()) { in checkRegisterCurDefs()
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| D | HexagonMCShuffler.cpp | 41 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo()); in init()
63 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
86 MCInst const &MI = I->getDesc(); in copyTo()
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCInstrInfo.cpp | 134 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, Inst); in deriveExtender()
170 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAccessSize()
178 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getBitCount()
185 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getCExtOpNum()
189 MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII, in getDesc() function in llvm::HexagonMCInstrInfo
251 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
269 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
275 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
283 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMaxValue()
298 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMinValue()
[all …]
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| D | HexagonShuffler.cpp | 132 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); in HexagonCVIResource()
133 setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore()); in HexagonCVIResource()
195 MCInst const *ID = ISJ->getDesc(); in check()
233 if (HexagonMCInstrInfo::getDesc(MCII, *ID).isReturn()) in check()
255 if (HexagonMCInstrInfo::getDesc(MCII, *ID).isBranch()) in check()
261 if (HexagonMCInstrInfo::getDesc(MCII, *ID).mayLoad()) in check()
285 MCInst const *ID = ISJ->getDesc(); in check()
294 if (HexagonMCInstrInfo::getDesc(MCII, *ID).getOpcode() != Hexagon::A2_nop) in check()
304 if (HexagonMCInstrInfo::getDesc(MCII, *ID).isBranch() || in check()
305 HexagonMCInstrInfo::getDesc(MCII, *ID).isCall()) in check()
[all …]
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| D | HexagonMCChecker.cpp | 57 const MCInstrDesc& MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init()
284 if (HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch() || in checkBranches()
285 HexagonMCInstrInfo::getDesc(MCII, MCI).isCall()) { in checkBranches()
287 if (HexagonMCInstrInfo::getDesc(MCII, MCI).isIndirectBranch() && in checkBranches()
301 if (HexagonMCInstrInfo::getDesc(MCII, MCI).isReturn() && in checkBranches()
302 HexagonMCInstrInfo::getDesc(MCII, MCI).mayLoad()) in checkBranches()
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| /external/skia/src/core/ |
| D | SkDescriptor.cpp | 148 this->reset(*that.getDesc()); in SkAutoDescriptor()
151 this->reset(*that.getDesc()); in operator =()
156 this->reset(*that.getDesc()); in SkAutoDescriptor()
164 this->reset(*that.getDesc()); in operator =()
199 SkDescriptor::ComputeChecksum(ad.getDesc()); in MakeFromBuffer()
201 if (SkDescriptor::ComputeChecksum(ad.getDesc()) != ad.getDesc()->fChecksum) { return {}; } in MakeFromBuffer()
203 if (!ad.getDesc()->isValid()) { return {}; } in MakeFromBuffer()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.cpp | 209 assert(LastInst.getDesc().isConditionalBranch() && in parseCondBranch()
256 if (J->getDesc().isUnconditionalBranch() || in analyzeBranch()
257 J->getDesc().isIndirectBranch()) { in analyzeBranch()
273 if (I->getDesc().isIndirectBranch()) in analyzeBranch()
281 if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) { in analyzeBranch()
287 if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) { in analyzeBranch()
293 if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() && in analyzeBranch()
294 I->getDesc().isUnconditionalBranch()) { in analyzeBranch()
312 if (!I->getDesc().isUnconditionalBranch() && in removeBranch()
313 !I->getDesc().isConditionalBranch()) in removeBranch()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMHazardRecognizer.cpp | 21 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
42 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
45 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMHazardRecognizer.cpp | 22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
43 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
46 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyCallIndirectFixup.cpp | 130 make_range(MI.operands_begin() + MI.getDesc().getNumDefs() + 1, in runOnMachineFunction()
133 Ops.push_back(MI.getOperand(MI.getDesc().getNumDefs())); in runOnMachineFunction()
136 while (MI.getNumOperands() > MI.getDesc().getNumDefs()) in runOnMachineFunction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 110 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps()
135 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass()
198 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
242 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() in computeOperandLatency()
327 unsigned SchedClass = MI->getDesc().getSchedClass(); in computeReciprocalThroughput()
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| D | ExecutionDomainFix.cpp | 237 const MCInstrDesc &MCID = MI->getDesc(); in processDefs()
259 for (unsigned i = mi->getDesc().getNumDefs(), in visitHardInstr()
260 e = mi->getDesc().getNumOperands(); in visitHardInstr()
271 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { in visitHardInstr()
290 for (unsigned i = mi->getDesc().getNumDefs(), in visitSoftInstr()
291 e = mi->getDesc().getNumOperands(); in visitSoftInstr()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86DiscriminateMemOps.cpp | 113 if (BypassPrefetchInstructions && IsPrefetchOpcode(MI.getDesc().Opcode)) in runOnMachineFunction()
129 if (X86II::getMemoryOperandNo(MI.getDesc().TSFlags) < 0) in runOnMachineFunction()
131 if (BypassPrefetchInstructions && IsPrefetchOpcode(MI.getDesc().Opcode)) in runOnMachineFunction()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 370 return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0; in SafeInForbiddenSlot()
376 return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0; in HasForbiddenSlot()
383 return MI.getDesc().getSize(); in GetInstSizeInBytes()
442 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) { in genInstrWithNewOpc()
453 for (unsigned J = 2, E = I->getDesc().getNumOperands(); J < E; ++J) { in genInstrWithNewOpc()
458 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) { in genInstrWithNewOpc()
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| /external/ow2-asm/asm-commons/src/main/java/org/objectweb/asm/commons/ |
| D | Remapper.java | 173 ? mapFieldName(handle.getOwner(), handle.getName(), handle.getDesc()) in mapValue()
174 : mapMethodName(handle.getOwner(), handle.getName(), handle.getDesc()), in mapValue()
175 isFieldHandle ? mapDesc(handle.getDesc()) : mapMethodDesc(handle.getDesc()), in mapValue()
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| /external/llvm/lib/Support/ |
| D | Statistic.cpp | 114 return std::strcmp(LHS->getDesc(), RHS->getDesc()) < 0; in sort()
142 Stats.Stats[i]->getDesc()); in PrintStatistics()
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| /external/desugar/java/com/google/devtools/build/android/desugar/ |
| D | LambdaDesugaring.java | 124 neededMethod.getDesc(), in visitEnd()
138 Type neededType = Type.getMethodType(neededMethod.getDesc()); in visitEnd()
147 original.getDesc(), in visitEnd()
265 invokedMethod.getTag(), internalName, name, invokedMethod.getDesc(), /*itf*/ false); in queueUpBridgeMethodIfNeeded()
274 invokedMethod.getDesc(), /*itf*/ in queueUpBridgeMethodIfNeeded()
284 Type.getArgumentTypes(invokedMethod.getDesc())); in queueUpBridgeMethodIfNeeded()
319 Type descriptor = Type.getMethodType(invokedMethod.getDesc()); in findTargetMethod()
662 asmHandle.getDesc(), in toMethodHandle()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 283 const MCInstrDesc &getDesc() const { return *MCID; }
338 operands_begin() + getDesc().getNumDefs());
343 operands_begin() + getDesc().getNumDefs());
348 return make_range(operands_begin() + getDesc().getNumDefs(),
353 return make_range(operands_begin() + getDesc().getNumDefs(),
357 return make_range(operands_begin() + getDesc().getNumDefs(),
361 return make_range(operands_begin() + getDesc().getNumDefs(),
407 return getDesc().getFlags() & (1 << MCFlag);
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| /external/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 79 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps()
105 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass()
168 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
212 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() in computeOperandLatency()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1355 const uint64_t F = MI.getDesc().TSFlags; in isPredicated()
1437 return MI.getDesc().isPredicable(); in isPredicable()
1466 if (MI.getDesc().isTerminator() || MI.isPosition()) in isSchedulingBoundary()
1707 const uint64_t F = MI->getDesc().TSFlags; in isAccumulator()
1719 && !(MI->getDesc().mayLoad()) in isComplex()
1720 && !(MI->getDesc().mayStore()) in isComplex()
1721 && (MI->getDesc().getOpcode() != Hexagon::S2_allocframe) in isComplex()
1722 && (MI->getDesc().getOpcode() != Hexagon::L2_deallocframe) in isComplex()
1811 if (!MI->getDesc().mayLoad() || !isPredicated(*MI)) in isConditionalLoad()
1902 const uint64_t F = MI->getDesc().TSFlags; in isConstExtended()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/HardwareUnits/ |
| D | LSUnit.cpp | 70 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in dispatch()
154 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in isAvailable()
172 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in onInstructionRetired()
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