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Searched refs:getKillRegState (Results 1 – 25 of 112) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRExpandPseudoInsts.cpp156 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandArith()
157 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandArith()
161 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandArith()
162 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expandArith()
189 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLogic()
190 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandLogic()
197 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandLogic()
198 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expandLogic()
237 .addReg(DstLoReg, getKillRegState(SrcIsKill)) in expandLogicImm()
247 .addReg(DstHiReg, getKillRegState(SrcIsKill)) in expandLogicImm()
[all …]
DAVRRelaxMemOperations.cpp112 .addReg(Src.getReg(), getKillRegState(Src.isKill())); in relax()
116 .addReg(Ptr.getReg(), getKillRegState(Ptr.isKill())); in relax()
DAVRInstrInfo.cpp53 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
62 .addReg(SrcLo, getKillRegState(KillSrc)); in copyPhysReg()
64 .addReg(SrcHi, getKillRegState(KillSrc)); in copyPhysReg()
78 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
155 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp323 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
331 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
335 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
346 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
363 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
367 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
411 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
414 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
417 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
420 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp320 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
328 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
332 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
343 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
360 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
364 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
408 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
411 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
414 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
417 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp52 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
62 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
70 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
97 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
DMLxExpansionPass.cpp291 .addReg(Src1Reg, getKillRegState(Src1Kill)) in ExpandFPMLxInstruction()
292 .addReg(Src2Reg, getKillRegState(Src2Kill)); in ExpandFPMLxInstruction()
302 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
303 .addReg(AccReg, getKillRegState(AccKill)); in ExpandFPMLxInstruction()
305 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
DARMLoadStoreOptimizer.cpp742 .addReg(Base, getKillRegState(KillOldBase)); in CreateLoadStoreMulti()
745 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
755 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
761 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
766 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
808 .addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti()
817 MIB.addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti()
823 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second)); in CreateLoadStoreMulti()
847 MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second)) in CreateLoadStoreDouble()
848 .addReg(Regs[1].first, getKillRegState(Regs[1].second)); in CreateLoadStoreDouble()
[all …]
/external/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp54 .addReg(SrcReg, getKillRegState(KillSrc))); in copyPhysReg()
64 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
91 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
DMLxExpansionPass.cpp294 .addReg(Src1Reg, getKillRegState(Src1Kill)) in ExpandFPMLxInstruction()
295 .addReg(Src2Reg, getKillRegState(Src2Kill)); in ExpandFPMLxInstruction()
305 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
306 .addReg(AccReg, getKillRegState(AccKill)); in ExpandFPMLxInstruction()
308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
DARMLoadStoreOptimizer.cpp707 .addReg(Base, getKillRegState(KillOldBase)); in CreateLoadStoreMulti()
710 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
720 .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset/4) in CreateLoadStoreMulti()
725 .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset) in CreateLoadStoreMulti()
729 .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset) in CreateLoadStoreMulti()
769 .addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti()
779 MIB.addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti()
785 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second)); in CreateLoadStoreMulti()
806 MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second)) in CreateLoadStoreDouble()
807 .addReg(Regs[1].first, getKillRegState(Regs[1].second)); in CreateLoadStoreDouble()
[all …]
/external/llvm/lib/Target/X86/
DX86InstrBuilder.h138 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
146 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
147 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFInstrInfo.cpp37 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
40 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
135 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
140 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp382 .addReg(Reg2, getKillRegState(Reg2IsKill)) in commuteInstructionImpl()
383 .addReg(Reg1, getKillRegState(Reg1IsKill)) in commuteInstructionImpl()
890 getKillRegState(KillSrc); in copyPhysReg()
902 getKillRegState(KillSrc); in copyPhysReg()
907 getKillRegState(KillSrc); in copyPhysReg()
949 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
951 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
970 getKillRegState(isKill)), in StoreRegToStackSlot()
976 getKillRegState(isKill)), in StoreRegToStackSlot()
981 getKillRegState(isKill)), in StoreRegToStackSlot()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrBuilder.h159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp1825 .addReg(Op0, getKillRegState(Op0IsKill)); in fastEmitInst_r()
1828 .addReg(Op0, getKillRegState(Op0IsKill)); in fastEmitInst_r()
1848 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rr()
1849 .addReg(Op1, getKillRegState(Op1IsKill)); in fastEmitInst_rr()
1852 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rr()
1853 .addReg(Op1, getKillRegState(Op1IsKill)); in fastEmitInst_rr()
1874 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rrr()
1875 .addReg(Op1, getKillRegState(Op1IsKill)) in fastEmitInst_rrr()
1876 .addReg(Op2, getKillRegState(Op2IsKill)); in fastEmitInst_rrr()
1879 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rrr()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp1892 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI); in copyPhysRegTuple()
1920 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
1923 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
1944 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
1949 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
1960 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
1970 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
2038 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
2042 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
2063 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
[all …]
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp78 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
114 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
148 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPImmInst()
191 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPConstInst()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
147 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPImmInst()
190 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPConstInst()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp2059 .addReg(Op0, getKillRegState(Op0IsKill)); in fastEmitInst_r()
2062 .addReg(Op0, getKillRegState(Op0IsKill)); in fastEmitInst_r()
2082 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rr()
2083 .addReg(Op1, getKillRegState(Op1IsKill)); in fastEmitInst_rr()
2086 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rr()
2087 .addReg(Op1, getKillRegState(Op1IsKill)); in fastEmitInst_rr()
2108 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rrr()
2109 .addReg(Op1, getKillRegState(Op1IsKill)) in fastEmitInst_rrr()
2110 .addReg(Op2, getKillRegState(Op2IsKill)); in fastEmitInst_rrr()
2113 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rrr()
[all …]
/external/llvm/lib/Target/BPF/
DBPFInstrInfo.cpp40 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
56 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp54 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
58 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
103 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp55 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
59 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
104 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp108 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
129 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4) in copyPhysReg()
135 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
176 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
247 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) in storeRegToStack()
580 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); in expandPseudoMTLoHi()
581 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); in expandPseudoMTLoHi()
591 unsigned KillSrc = getKillRegState(Src.isKill()); in expandCvtFPInt()
/external/llvm/lib/Target/Hexagon/
DHexagonNewValueJump.cpp646 .addReg(cmpReg1, getKillRegState(MO1IsKill)) in runOnMachineFunction()
647 .addReg(cmpOp2, getKillRegState(MO2IsKill)) in runOnMachineFunction()
657 .addReg(cmpReg1, getKillRegState(MO1IsKill)) in runOnMachineFunction()
663 .addReg(cmpReg1, getKillRegState(MO1IsKill)) in runOnMachineFunction()

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