Searched refs:getRegBitWidth (Results 1 – 15 of 15) sorted by relevance
94 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub)); in mask()273 assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch"); in evaluate()313 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0; in evaluate()371 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()700 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()755 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32); in evaluate()767 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32); in evaluate()829 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()861 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()966 uint16_t RW = getRegBitWidth(PD); in evaluate()[all …]
329 uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const { in getRegBitWidth() function in BT::MachineEvaluator350 uint16_t BW = getRegBitWidth(RR); in getCell()709 uint16_t W = getRegBitWidth(Reg); in mask()734 uint16_t W = getRegBitWidth(RD); in evaluate()748 uint16_t WD = getRegBitWidth(RD); in evaluate()749 uint16_t WS = getRegBitWidth(RS); in evaluate()806 uint16_t DefBW = ME.getRegBitWidth(DefRR); in visitPHI()884 uint16_t DefBW = ME.getRegBitWidth(RD); in visitNonBranch()
1856 unsigned getRegBitWidth(unsigned Reg) const;1993 unsigned W = getRegBitWidth(DefR.Reg); in evaluate()2154 unsigned BW = getRegBitWidth(R1.Reg); in evaluate()2361 unsigned HexagonConstEvaluator::getRegBitWidth(unsigned Reg) const { in getRegBitWidth() function in HexagonConstEvaluator2699 unsigned W = getRegBitWidth(DefR.Reg); in evaluateHexCondMove()2753 unsigned BW = getRegBitWidth(DefR.Reg); in evaluateHexExt()2899 unsigned W = getRegBitWidth(R); in rewriteHexConstDefs()
396 uint16_t getRegBitWidth(const RegisterRef &RR) const;
84 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub)); in mask()201 assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch"); in evaluate()241 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0; in evaluate()297 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()626 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()680 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32); in evaluate()692 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32); in evaluate()754 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()775 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()1075 uint16_t W = getRegBitWidth(RD); in evaluateLoad()
314 uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const { in getRegBitWidth() function in BT::MachineEvaluator342 uint16_t BW = getRegBitWidth(RR); in getCell()731 uint16_t W = getRegBitWidth(Reg); in mask()750 uint16_t W = getRegBitWidth(RD); in evaluate()764 uint16_t WD = getRegBitWidth(RD); in evaluate()765 uint16_t WS = getRegBitWidth(RS); in evaluate()793 uint16_t DefBW = ME.getRegBitWidth(DefRR); in visitPHI()874 uint16_t DefBW = ME.getRegBitWidth(RD); in visitNonBranch()
347 uint16_t getRegBitWidth(const RegisterRef &RR) const;
128 if (AMDGPU::getRegBitWidth(IdxRC->getID()) != 64) in findSRegBaseAndIndex()138 if (AMDGPU::getRegBitWidth(BaseRC->getID()) != 64) in findSRegBaseAndIndex()
638 unsigned NumSubRegs = AMDGPU::getRegBitWidth(RC->getID()) / (EltSize * CHAR_BIT); in buildSpillLoadStore()1546 switch (AMDGPU::getRegBitWidth(*RC->MC)) { in getRegSplitParts()1597 switch (AMDGPU::getRegBitWidth(*RC->MC)) { in getRegSplitParts()1638 switch (AMDGPU::getRegBitWidth(*RC->MC)) { in getRegSplitParts()1666 switch (AMDGPU::getRegBitWidth(*RC->MC)) { in getRegSplitParts()
693 if (AMDGPU::getRegBitWidth(VDataRCID) > 64 && in createsVALUHazard()705 AMDGPU::getRegBitWidth(Desc.OpInfo[SRsrcIdx].RegClass) == 256); in createsVALUHazard()711 if (AMDGPU::getRegBitWidth(Desc.OpInfo[DataIdx].RegClass) > 64) in createsVALUHazard()
867 if (UseOp.getSubReg() && AMDGPU::getRegBitWidth(FoldRC->getID()) == 64) { in foldOperand()871 if (AMDGPU::getRegBitWidth(UseRC->getID()) != 64) in foldOperand()
2138 int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32; in canInsertSelect()2152 int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32; in canInsertSelect()
586 unsigned getRegBitWidth(unsigned RCID);589 unsigned getRegBitWidth(const MCRegisterClass &RC);
1083 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth() function1132 unsigned getRegBitWidth(const MCRegisterClass &RC) { in getRegBitWidth() function1133 return getRegBitWidth(RC.getID()); in getRegBitWidth()1140 return getRegBitWidth(MRI->getRegClass(RCID)) / 8; in getRegOperandSize()
580 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); in printOperand()