Searched refs:get_bar_addr (Results 1 – 6 of 6) sorted by relevance
197 let mmio_addr = self.config_regs.get_bar_addr(PVPANIC_REG_NUM as usize); in read_bar()206 let mmio_addr = self.config_regs.get_bar_addr(PVPANIC_REG_NUM as usize); in write_bar()287 let mmio_addr = device.config_regs.get_bar_addr(PVPANIC_REG_NUM as usize); in pvpanic_read_write()
382 let bar0 = self.config_regs.get_bar_addr(0); in read_bar()383 let bar1 = self.config_regs.get_bar_addr(1); in read_bar()394 let bar0 = self.config_regs.get_bar_addr(0); in write_bar()395 let bar1 = self.config_regs.get_bar_addr(1); in write_bar()
594 config.addr = self.get_bar_addr(bar_num); in get_bar_configuration()607 pub fn get_bar_addr(&self, bar_num: PciBarIndex) -> u64 { in get_bar_addr() method910 assert_eq!(cfg.get_bar_addr(0), 0); in query_unused_bar()945 assert_eq!(cfg.get_bar_addr(0), 0x0123_4567_89AB_CDE0); in add_pci_bar_mem_64bit()992 assert_eq!(cfg.get_bar_addr(0), 0x12345670); in add_pci_bar_mem_32bit()1035 assert_eq!(cfg.get_bar_addr(0), 0x1230); in add_pci_bar_io()1294 assert_eq!(cfg.get_bar_addr(ROM_BAR_IDX), 0x12345000); in add_rom_bar()
1287 let bar = self.config_regs.get_bar_addr(COIOMMU_MMIO_BAR as usize); in read_mmio()1322 let bar = self.config_regs.get_bar_addr(COIOMMU_MMIO_BAR as usize); in write_mmio()1539 let mmio_bar = self.config_regs.get_bar_addr(COIOMMU_MMIO_BAR as usize); in read_bar()1542 .get_bar_addr(COIOMMU_NOTIFYMAP_BAR as usize); in read_bar()1558 let mmio_bar = self.config_regs.get_bar_addr(COIOMMU_MMIO_BAR as usize); in write_bar()1561 .get_bar_addr(COIOMMU_NOTIFYMAP_BAR as usize); in write_bar()1577 let bar0 = self.config_regs.get_bar_addr(COIOMMU_MMIO_BAR as usize); in ioevents()
292 let bar0 = self.config_regs.get_bar_addr(0); in read_bar()308 let bar0 = self.config_regs.get_bar_addr(0); in write_bar()
745 let bar0 = self.config_regs.get_bar_addr(self.settings_bar as usize); in ioevents()