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Searched refs:get_tiling (Results 1 – 9 of 9) sorted by relevance

/external/igt-gpu-tools/lib/
Dioctl_wrappers.c150 struct drm_i915_gem_get_tiling get_tiling; in gem_get_tiling() local
152 memset(&get_tiling, 0, sizeof(get_tiling)); in gem_get_tiling()
153 get_tiling.handle = handle; in gem_get_tiling()
155 igt_assert_eq(__gem_get_tiling(fd, &get_tiling), 0); in gem_get_tiling()
157 *tiling = get_tiling.tiling_mode; in gem_get_tiling()
158 *swizzle = get_tiling.swizzle_mode; in gem_get_tiling()
160 return get_tiling.phys_swizzle_mode == get_tiling.swizzle_mode; in gem_get_tiling()
/external/mesa3d/src/intel/vulkan/
Danv_gem.c230 struct drm_i915_gem_get_tiling get_tiling = { in anv_gem_get_tiling() local
239 if (gen_ioctl(device->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling)) { in anv_gem_get_tiling()
244 return get_tiling.tiling_mode; in anv_gem_get_tiling()
338 struct drm_i915_gem_get_tiling get_tiling = { in anv_gem_get_bit6_swizzle() local
342 if (gen_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling)) { in anv_gem_get_bit6_swizzle()
347 swizzled = get_tiling.swizzle_mode != I915_BIT_6_SWIZZLE_NONE; in anv_gem_get_bit6_swizzle()
/external/igt-gpu-tools/tests/i915/
Dgem_tiled_wb.c114 get_tiling(int fd, uint32_t handle, uint32_t *tiling, uint32_t *swizzle) in get_tiling() function
144 get_tiling(fd, handle, &tiling, &swizzle);
/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_resource.c628 struct drm_vc4_get_tiling get_tiling = { in vc4_resource_from_handle() local
631 int ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_TILING, &get_tiling); in vc4_resource_from_handle()
636 whandle->modifier = get_tiling.modifier; in vc4_resource_from_handle()
637 } else if (whandle->modifier != get_tiling.modifier) { in vc4_resource_from_handle()
640 (long long)whandle->modifier, get_tiling.modifier); in vc4_resource_from_handle()
1135 struct drm_vc4_get_tiling get_tiling = { in vc4_resource_screen_init() local
1138 int ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_TILING, &get_tiling); in vc4_resource_screen_init()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_bufmgr.c824 struct drm_i915_gem_get_tiling get_tiling = { .handle = bo->gem_handle }; in brw_bo_gem_create_from_name() local
825 ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling); in brw_bo_gem_create_from_name()
829 bo->tiling_mode = get_tiling.tiling_mode; in brw_bo_gem_create_from_name()
830 bo->swizzle_mode = get_tiling.swizzle_mode; in brw_bo_gem_create_from_name()
1524 struct drm_i915_gem_get_tiling get_tiling = { .handle = bo->gem_handle }; in brw_bo_gem_create_from_prime_internal() local
1525 if (drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling)) in brw_bo_gem_create_from_prime_internal()
1528 bo->tiling_mode = get_tiling.tiling_mode; in brw_bo_gem_create_from_prime_internal()
1529 bo->swizzle_mode = get_tiling.swizzle_mode; in brw_bo_gem_create_from_prime_internal()
/external/mesa3d/src/gallium/drivers/iris/
Diris_bufmgr.c727 struct drm_i915_gem_get_tiling get_tiling = { .handle = bo->gem_handle }; in iris_bo_gem_create_from_name() local
728 ret = gen_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling); in iris_bo_gem_create_from_name()
732 bo->tiling_mode = get_tiling.tiling_mode; in iris_bo_gem_create_from_name()
1449 struct drm_i915_gem_get_tiling get_tiling = { .handle = bo->gem_handle }; in iris_bo_import_dmabuf() local
1450 if (gen_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling)) in iris_bo_import_dmabuf()
1452 bo->tiling_mode = get_tiling.tiling_mode; in iris_bo_import_dmabuf()
/external/mesa3d/src/intel/dev/
Dgen_device_info.c1359 struct drm_i915_gem_get_tiling get_tiling = { in gen_has_get_tiling() local
1362 ret = gen_ioctl(fd, DRM_IOCTL_I915_GEM_SET_TILING, &get_tiling); in gen_has_get_tiling()
/external/libdrm/intel/
Dintel_bufmgr_gem.c1038 struct drm_i915_gem_get_tiling get_tiling = { in get_tiling_mode() local
1045 &get_tiling); in get_tiling_mode()
1049 *tiling_mode = get_tiling.tiling_mode; in get_tiling_mode()
1050 *swizzle_mode = get_tiling.swizzle_mode; in get_tiling_mode()
/external/mesa3d/docs/relnotes/
D20.2.0.rst3776 - iris/bufmgr: Do not use map_gtt or use set/get_tiling on DG1