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Searched refs:hasReg (Results 1 – 25 of 25) sorted by relevance

/external/swiftshader/third_party/subzero/src/
DIceInstX8632.cpp545 if (Var->hasReg()) { in emitIAS()
604 if (Var->hasReg()) { in emitIAS()
659 if (Var->hasReg()) { in emitIASOpTyGPR()
680 assert(Var->hasReg()); in emitIASRegOpTyGPR()
685 if (SrcVar->hasReg()) { in emitIASRegOpTyGPR()
723 assert(SrcVar->hasReg()); in emitIASAddrOpTyGPR()
744 assert(!Op0Var->hasReg()); in emitIASAsAddrOpTyGPR()
763 assert(Var->hasReg()); in emitIASGPRShift()
768 assert(SrcVar->hasReg()); in emitIASGPRShift()
783 assert(Dest->hasReg()); in emitIASGPRShiftDouble()
[all …]
DIceInstX8664.cpp532 if (Var->hasReg()) { in emitIAS()
591 if (Var->hasReg()) { in emitIAS()
646 if (Var->hasReg()) { in emitIASOpTyGPR()
667 assert(Var->hasReg()); in emitIASRegOpTyGPR()
672 if (SrcVar->hasReg()) { in emitIASRegOpTyGPR()
711 assert(SrcVar->hasReg()); in emitIASAddrOpTyGPR()
735 assert(!Op0Var->hasReg()); in emitIASAsAddrOpTyGPR()
752 assert(Var->hasReg()); in emitIASGPRShift()
757 assert(SrcVar->hasReg()); in emitIASGPRShift()
775 assert(Dest->hasReg()); in emitIASGPRShiftDouble()
[all …]
DIceCfgNode.cpp374 if (!Var1->hasReg()) in sameVarOrReg()
376 if (!Var2->hasReg()) in sameVarOrReg()
525 if (Var->hasReg()) in advancedPhiLowering()
527 if (!Item.Dest->hasReg()) in advancedPhiLowering()
973 if (!Var->hasReg()) in emitRegisterUsage()
1012 if (!Instr->isDestRedefined() && Dest && Dest->hasReg()) in emitLiveRangesEnded()
1016 if (ShouldReport && Var->hasReg()) { in emitLiveRangesEnded()
1044 if (!Dest->hasReg()) in updateStats()
1049 if (!Src->hasReg()) in updateStats()
1109 if (DecorateAsm && Dest->hasReg()) { in emit()
[all …]
DIceInstARM32.cpp1307 if (!Reg->hasReg()) { in validatePushOrPopRegisterListOrDie()
1389 assert(Before->hasReg()); in isAssignedConsecutiveRegisters()
1390 assert(After->hasReg()); in isAssignedConsecutiveRegisters()
1409 assert(Var->hasReg() && "stack op only applies to registers"); in emitUsingForm()
1434 assert(NextReg->hasReg()); in emitUsingForm()
1561 assert(Src->hasReg()); in getDRegister()
1618 assert(Src->hasReg()); in getSRegister()
1833 assert(DestHi->hasReg()); in emitMultiDestSingleSource()
1834 assert(DestLo->hasReg()); in emitMultiDestSingleSource()
1835 assert(Src->hasReg()); in emitMultiDestSingleSource()
[all …]
DIceRegAlloc.cpp133 if (Var->hasReg()) { in initForGlobal()
226 if (Var->hasReg() || Var->mustHaveReg()) { in initForInfOnly()
235 (Var->hasReg() || Var->mustHaveReg())) { in initForInfOnly()
260 if (Var->hasReg()) { in initForInfOnly()
311 if (Var->hasReg()) { in initForSecondChance()
598 assert(Item->hasReg()); in filterFreeWithPrecoloredRanges()
865 if (Iter.Cur->hasReg()) { in scan()
DIceInstMIPS32.cpp333 assert(RA->hasReg()); in emit()
518 assert(RA->hasReg()); in emitIAS()
545 const bool DestIsReg = Dest->hasReg(); in emit()
546 const bool SrcIsReg = (SrcV && SrcV->hasReg()); in emit()
602 const bool DestIsReg = Dest->hasReg(); in emitIAS()
603 const bool SrcIsReg = (SrcV && SrcV->hasReg()); in emitIAS()
DIceOperand.cpp569 (!hasReg() && !Func->getTarget()->hasComputedFrame())) { in dump()
576 if (hasReg()) { in dump()
584 hasReg() ? getBaseRegNum() : Func->getTarget()->getFrameOrStackReg(); in dump()
DIceVariableSplitting.cpp34 return !Var->hasReg() && Var->mayHaveReg(); in isAllocable()
41 return Var->hasReg() || Var->mustHaveReg(); in isInf()
DIceTargetLowering.cpp544 if (!Var->mustNotHaveReg() && !Var->hasReg()) { in postRegallocSplitting()
616 if (!ExtraVar->hasReg()) { in postRegallocSplitting()
770 if (Var->hasReg()) { in getVarStackSlotParams()
783 if (!Var->hasReg()) { in getVarStackSlotParams()
DIceLiveness.cpp105 (!IsFullInit && !Var->hasReg() && !Var->mustHaveReg())) in initInternal()
DIceInst.cpp1029 if (Dest->hasReg() && Dest->getRegNum() == SrcVar->getRegNum()) { in checkForRedundantAssign()
1034 if (!Dest->hasReg() && !SrcVar->hasReg()) { in checkForRedundantAssign()
1049 if (SrcVar->hasReg() && Dest->hasStackOffset() && in checkForRedundantAssign()
DIceOperand.h741 bool hasReg() const { return getRegNum().hasValue(); } in hasReg() function
745 assert(!hasReg() || RegNum == NewRegNum); in setRegNum()
829 if (!Root->hasReg() && Root->hasStackOffset()) { in getLinkedToStackRoot()
DIceAssemblerMIPS32.cpp126 assert(Var->hasReg() && isScalarIntegerType(Var->getType())); in getEncodedGPRegNum()
132 assert(Var->hasReg() && isScalarFloatingType(Var->getType())); in getEncodedFPRegNum()
147 if (Var->hasReg()) { in encodeOperand()
DIceTargetLoweringARM32.cpp392 assert(!Var64->hasReg() || Var64->mustHaveReg()); in copyRegAllocFromInfWeightVariable64On32()
393 if (!Var64->hasReg()) { in copyRegAllocFromInfWeightVariable64On32()
401 assert(Lo->hasReg() == Hi->hasReg()); in copyRegAllocFromInfWeightVariable64On32()
402 if (Lo->hasReg()) { in copyRegAllocFromInfWeightVariable64On32()
1076 if (Var->hasReg()) { in emitVariable()
1261 if (!Arg->hasReg()) { in finishArgumentLowering()
1691 if (!Dest->hasReg()) { in legalizeMov()
1693 assert(SrcR->hasReg()); in legalizeMov()
1718 if (!Var->hasReg()) { in legalizeMov()
3363 if (Dest->hasReg()) { in lowerAssign()
[all …]
DIceTargetLoweringMIPS32.cpp1125 if (Var->hasReg()) { in emitVariable()
1453 if (!Arg->hasReg()) { in finishArgumentLowering()
1844 if (Dest->hasReg() && SrcR->hasReg()) { in legalizeMov()
1932 if (!Dest->hasReg()) { in legalizeMov()
1934 assert(SrcR->hasReg()); in legalizeMov()
1999 if (!Var->hasReg()) { in legalizeMov()
3039 if (Dest->hasReg()) { in lowerAssign()
5816 !Subst->hasReg()) { in legalize()
5933 bool MustHaveRegister = (Var->hasReg() || Var->mustHaveReg()); in legalize()
DIceAssemblerARM32.cpp179 assert(Var->hasReg()); in getEncodedGPRegNum()
186 assert(Var->hasReg()); in getEncodedSRegNum()
356 if (Var->hasReg()) { in encodeOperand()
486 if (Var->hasReg()) in encodeAddress()
492 Var->hasReg() ? Var->getBaseRegNum() : TInfo.FrameOrStackReg; in encodeAddress()
499 if (!Var->hasReg()) in encodeAddress()
DIceTargetLoweringX8664.cpp808 if (Var->hasReg()) { in emitVariable()
907 assert(!Root->hasReg()); in addProlog()
908 if (!Root->hasReg()) { in addProlog()
1132 if (Arg->hasReg()) { in finishArgumentLowering()
5682 if (Dest->hasReg()) { in lowerMove()
6605 if (Subst->mustHaveReg() && !Subst->hasReg()) { in legalize()
6706 bool MustHaveRegister = (Var->hasReg() || Var->mustHaveReg()); in legalize()
6773 if (Var->hasReg()) in legalizeSrc0ForCmp()
DIceTargetLoweringX8632.cpp798 if (Var->hasReg()) { in emitVariable()
895 assert(!Root->hasReg()); in addProlog()
896 if (!Root->hasReg()) { in addProlog()
1149 if (Arg->hasReg()) { in finishArgumentLowering()
6294 if (Dest->hasReg()) { in lowerMove()
7343 if (Subst->mustHaveReg() && !Subst->hasReg()) { in legalize()
7433 bool MustHaveRegister = (Var->hasReg() || Var->mustHaveReg()); in legalize()
7501 if (Var->hasReg()) in legalizeSrc0ForCmp()
DIceAssemblerX8632.cpp33 if (Var->hasReg()) in AsmAddress()
111 assert(!Split->getVar()->hasReg()); in AsmAddress()
DIceInstX8632.h1128 if (SrcVar->hasReg() && this->Dest->hasReg()) { in isRedundantAssign()
DIceInstX8664.h1067 if (SrcVar->hasReg() && this->Dest->hasReg()) { in isRedundantAssign()
DIceAssemblerX8664.cpp33 if (Var->hasReg()) in AsmAddress()
/external/llvm/lib/Target/AMDGPU/
DSIMachineFunctionInfo.h129 bool hasReg() { return VGPR != AMDGPU::NoRegister;} in hasReg() function
DSIRegisterInfo.cpp531 if (Spill.hasReg()) { in eliminateFrameIndex()
595 if (Spill.hasReg()) { in eliminateFrameIndex()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIMachineFunctionInfo.h439 bool hasReg() { return VGPR != 0;}