| /external/zucchini/ |
| D | arm_utils.cc | 317 uint32_t imm10 = GetUnsignedBits<16, 25>(code32); // ii...i. in DecodeT24() local
319 uint32_t t = (imm10 << 12) | (imm11 << 1); in DecodeT24()
354 uint32_t imm10 = GetUnsignedBits<12, 21>(disp); // ii...i. in EncodeT24() local
359 t |= (S << 26) | (imm10 << 16) | ((I1 ^ S ^ 1) << 13) | in EncodeT24()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16InstrFormats.td | 429 // <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
480 // <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
504 // <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>
529 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
582 // <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>
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| D | MipsInstrFormats.td | 609 bits<10> imm10;
616 let Inst{15-6} = imm10;
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| D | Mips64InstrInfo.td | 378 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
379 !strconcat(opstr, "\t$rt, $rs, $imm10"),
381 immSExt10_64:$imm10)))],
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | Mips16InstrFormats.td | 428 // <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
479 // <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
503 // <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>
528 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
581 // <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>
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| D | MipsInstrFormats.td | 614 bits<10> imm10;
621 let Inst{15-6} = imm10;
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| D | Mips64InstrInfo.td | 480 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
481 !strconcat(opstr, "\t$rt, $rs, $imm10"),
483 immSExt10_64:$imm10)))],
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.td | 113 def imm10 : Operand<i32>, PatLeaf<(imm), [{
226 let MIOperandInfo = (ops GPR:$base, imm10:$offset, AluOp:$Opcode);
565 let imm10 = src{9-0};
664 let imm10 = dst{9-0};
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| D | LanaiInstrFormats.td | 509 bits<10> imm10;
520 let Inst{9 - 0} = imm10;
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.td | 113 def imm10 : Operand<i32>, PatLeaf<(imm), [{
229 let MIOperandInfo = (ops GPR:$base, imm10:$offset, AluOp:$Opcode);
568 let imm10 = src{9-0};
667 let imm10 = dst{9-0};
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| D | LanaiInstrFormats.td | 510 bits<10> imm10;
521 let Inst{9 - 0} = imm10;
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| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 7233 static Instr ImmLSPAC(int64_t imm10) { in ImmLSPAC() argument
7234 VIXL_ASSERT(IsMultiple(imm10, 1 << 3)); in ImmLSPAC()
7235 int64_t scaled_imm10 = imm10 / (1 << 3); in ImmLSPAC()
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| /external/capstone/arch/ARM/ |
| D | ARMDisassembler.c | 2241 unsigned imm10 = fieldFromInstruction_4(Insn, 16, 10); in DecodeT2BInstruction() local
2243 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; in DecodeT2BInstruction()
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 2275 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); in DecodeT2BInstruction() local
2277 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; in DecodeT2BInstruction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 2627 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); in DecodeT2BInstruction() local
2629 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; in DecodeT2BInstruction()
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenDAGISel.inc | 14958 /* 27598*/ OPC_RecordChild1, // #1 = $imm10
14972 …GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] })<<P:Predicate_immSExt10_64>>:$imm10, SETEQ:{ *:[Other]…
14973 // Dst: (SEQi:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$imm10)
14982 …GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] })<<P:Predicate_immSExt10_64>>:$imm10, SETNE:{ *:[Other]…
14983 // Dst: (SNEi:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$imm10)
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| D | MipsGenMCCodeEmitter.inc | 6337 // op: imm10
|