| /external/pcre/src/sljit/ |
| D | sljitNativeARM_T2_32.c | 602 sljit_uw imm, imm2; in emit_op_imm() local
632 imm2 = NEGATE(imm); in emit_op_imm()
636 if (imm2 <= 0x7) in emit_op_imm()
637 return push_inst16(compiler, SUBSI3 | IMM3(imm2) | RD3(dst) | RN3(reg)); in emit_op_imm()
641 if (imm2 <= 0xff) in emit_op_imm()
642 return push_inst16(compiler, SUBSI8 | IMM8(imm2) | RDN3(dst)); in emit_op_imm()
648 if (imm2 <= 0xfff) in emit_op_imm()
649 return push_inst32(compiler, SUBWI | RD4(dst) | RN4(reg) | IMM12(imm2)); in emit_op_imm()
651 imm2 = get_imm(imm); in emit_op_imm()
652 if (imm2 != INVALID_IMM) in emit_op_imm()
[all …]
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| D | sljitNativeARM_32.c | 1246 sljit_uw imm2 = get_imm(imm); in emit_add_sp() local
1248 if (imm2 == 0) { in emit_add_sp()
1249 imm2 = (imm & ~(sljit_uw)0x3ff) >> 10; in emit_add_sp()
1252 FAIL_IF(push_inst(compiler, ADD | SRC2_IMM | RD(SLJIT_SP) | RN(SLJIT_SP) | 0xb00 | imm2)); in emit_add_sp()
1256 return push_inst(compiler, ADD | RD(SLJIT_SP) | RN(SLJIT_SP) | imm2); in emit_add_sp()
1663 sljit_uw imm2; in generate_int() local
1706 imm2 = SRC2_IMM | ((imm >> 8) & 0xff) | (((rol + 8) & 0xf) << 8); in generate_int()
1729 imm2 = SRC2_IMM | (imm >> 24) | ((rol & 0xf) << 8); in generate_int()
1759 imm2 = SRC2_IMM | (imm >> 24) | ((rol & 0xf) << 8); in generate_int()
1765 FAIL_IF(push_inst(compiler, (positive ? ORR : BIC) | RD(reg) | RN(reg) | imm2)); in generate_int()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips32r6InstrFormats.td | 493 bits<2> imm2;
502 let Inst{7-6} = imm2;
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| D | MicroMips32r6InstrFormats.td | 412 bits<2> imm2;
420 let Inst{10-9} = imm2;
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| D | Mips32r6InstrInfo.td | 671 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
672 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2");
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| D | MicroMips32r6InstrInfo.td | 543 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
544 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
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| D | MipsFastISel.cpp | 188 uint64_t imm2, unsigned Op3, bool Op3IsKill) { in fastEmitInst_riir() argument
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | Mips32r6InstrFormats.td | 508 bits<2> imm2;
517 let Inst{7-6} = imm2;
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| D | MicroMips32r6InstrFormats.td | 362 bits<2> imm2;
370 let Inst{10-9} = imm2;
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| D | Mips32r6InstrInfo.td | 749 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
750 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2");
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| D | MicroMips32r6InstrInfo.td | 553 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
554 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
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| D | MipsFastISel.cpp | 238 uint64_t imm2, unsigned Op3, bool Op3IsKill) { in fastEmitInst_riir() argument
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| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_peephole.cpp | 788 ImmediateValue &imm2) in expr() argument
790 struct Storage *const a = &imm0.reg, *const b = &imm1.reg, *const c = &imm2.reg; in expr()
904 const int s, ImmediateValue& imm2) in tryCollapseChainedMULs() argument
910 float f = imm2.reg.data.f32 * exp2f(mul2->postFactor); in tryCollapseChainedMULs()
968 ConstantFolding::opnd3(Instruction *i, ImmediateValue &imm2) in opnd3() argument
973 if (imm2.isInteger(0)) { in opnd3()
981 if (imm2.isInteger(0)) { in opnd3()
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| /external/vixl/test/aarch64/ |
| D | test-simulator-aarch64.cc | 210 const VRegister& vd, int imm1, const VRegister& vn, int imm2);
2781 for (unsigned imm2 = 0; imm2 < inputs_imm2_length; imm2++) { in TestOpImmOpImmNEON() local
2790 (imm2 * vd_lane_count) + lane; in TestOpImmOpImmNEON()
2817 (imm2 * vd_lane_count) + lane; in TestOpImmOpImmNEON()
2822 unsigned input_index_imm2 = imm2; in TestOpImmOpImmNEON()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 265 // t2addrmode_so_reg := reg + (reg << imm2)
602 let Inst{7-6} = 0b00; // imm2
686 let Inst{7-6} = 0b00; // imm2
807 let Inst{7-6} = 0b00; // imm2
849 let Inst{7-6} = 0b00; // imm2
947 let Inst{7-6} = 0b00; // imm2
1670 let Inst{5-4} = addr{1-0}; // imm2
2261 let Inst{7-6} = 0b00; // imm2 = '00'
2284 let Inst{7-6} = 0b00; // imm2 = '00'
2489 let Inst{7-6} = 0b00; // imm2
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1571 MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32 in processInstruction() local
1572 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2); in processInstruction()
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1795 MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32 in processInstruction() local
1796 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2); in processInstruction()
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| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 7297 static Instr ImmBarrierDomain(int imm2) { in ImmBarrierDomain() argument
7298 VIXL_ASSERT(IsUint2(imm2)); in ImmBarrierDomain()
7299 return imm2 << ImmBarrierDomain_offset; in ImmBarrierDomain()
7302 static Instr ImmBarrierType(int imm2) { in ImmBarrierType() argument
7303 VIXL_ASSERT(IsUint2(imm2)); in ImmBarrierType()
7304 return imm2 << ImmBarrierType_offset; in ImmBarrierType()
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| D | disasm-aarch64.cc | 3935 int imm2 = instr->ExtractBits(23, 22); in VisitSVEBroadcastIndexElement() local
3936 if ((CountSetBits(imm2) + CountSetBits(tsz)) == 1) { in VisitSVEBroadcastIndexElement()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 336 // t2addrmode_so_reg := reg + (reg << imm2)
756 let Inst{7-6} = 0b00; // imm2
842 let Inst{7-6} = 0b00; // imm2
999 let Inst{7-6} = 0b00; // imm2
1041 let Inst{7-6} = 0b00; // imm2
1140 let Inst{7-6} = 0b00; // imm2
1864 let Inst{5-4} = addr{1-0}; // imm2
2796 let Inst{7-6} = 0b00; // imm2
3317 let Inst{7-6} = 0b00; // imm2
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | README-SSE.txt | 467 INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
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| /external/llvm/lib/Target/X86/ |
| D | README-SSE.txt | 467 INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrFormats.td | 3033 ImmOpWithPattern imm1, ImmOpWithPattern imm2>
3034 : InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCCodeEmitter.inc | 4943 // op: imm2
5192 // op: imm2
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXIntrinsics.td | 86 def imm2 : NVPTXInst<
963 def imm2 : NVPTXInst<(outs regclass:$dst),
|