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Searched refs:imm3 (Results 1 – 23 of 23) sorted by relevance

/external/mesa3d/src/compiler/glsl/
Dlower_blend_equation_advanced.cpp37 #define imm3(x) new(mem_ctx) ir_constant((float) (x), 3) macro
61 ir_rvalue *rule_1 = mul(imm3(2), mul(src, dst)); in blend_overlay()
63 sub(imm3(1), mul(imm3(2), mul(sub(imm3(1), src), sub(imm3(1), dst)))); in blend_overlay()
64 return csel(lequal(dst, imm3(0.5f)), rule_1, rule_2); in blend_overlay()
91 return csel(lequal(dst, imm3(0)), imm3(0), in blend_colordodge()
92 csel(gequal(src, imm3(1)), imm3(1), in blend_colordodge()
93 min2(imm3(1), div(dst, sub(imm3(1), src))))); in blend_colordodge()
106 return csel(gequal(dst, imm3(1)), imm3(1), in blend_colorburn()
107 csel(lequal(src, imm3(0)), imm3(0), in blend_colorburn()
108 sub(imm3(1), min2(imm3(1), div(sub(imm3(1), dst), src))))); in blend_colorburn()
[all …]
/external/vixl/test/aarch32/config/
Dcond-rdlow-rnlow-operand-immediate-t32.json29 // MNEMONIC{<c>}.N <Rd>, <Rn>, #<imm3>
34 "Add", // ADD<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
37 "Adds", // ADDS{<q>} <Rd>, <Rn>, #<imm3> ; T1
42 "Sub", // SUB<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
45 "Subs" // SUBS{<q>} <Rd>, <Rn>, #<imm3> ; T1
174 "Adds", // ADDS{<q>} <Rd>, <Rn>, #<imm3> ; T1
175 "Subs" // SUBS{<q>} <Rd>, <Rn>, #<imm3> ; T1
191 "Add", // ADD<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
192 "Sub" // SUB<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb.td955 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
957 "add", "\t$Rd, $Rm, $imm3",
958 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
960 bits<3> imm3;
961 let Inst{8-6} = imm3;
993 def tADDSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
996 imm0_7:$imm3))]>,
1298 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1300 "sub", "\t$Rd, $Rm, $imm3",
1301 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
[all …]
DARMInstrThumb2.td755 let Inst{14-12} = 0b000; // imm3
841 let Inst{14-12} = 0b000; // imm3
998 let Inst{14-12} = 0b000; // imm3
1040 let Inst{14-12} = 0b000; // imm3
1138 let Inst{14-12} = 0b000; // imm3
2795 let Inst{14-12} = 0b000; // imm3
3315 let Inst{14-12} = 0b000; // imm3
/external/llvm/lib/Target/ARM/
DARMInstrThumb.td916 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
918 "add", "\t$Rd, $Rm, $imm3",
919 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
921 bits<3> imm3;
922 let Inst{8-6} = imm3;
1203 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1205 "sub", "\t$Rd, $Rm, $imm3",
1206 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
1208 bits<3> imm3;
1209 let Inst{8-6} = imm3;
DARMInstrThumb2.td601 let Inst{14-12} = 0b000; // imm3
685 let Inst{14-12} = 0b000; // imm3
806 let Inst{14-12} = 0b000; // imm3
848 let Inst{14-12} = 0b000; // imm3
945 let Inst{14-12} = 0b000; // imm3
2260 let Inst{14-12} = 0b000; // imm3 = '000'
2283 let Inst{14-12} = 0b000; // imm3 = '000'
2488 let Inst{14-12} = 0b000; // imm3
3106 let Inst{14-12} = 0b000; // imm3
/external/vixl/src/aarch64/
Dmacro-assembler-sve-aarch64.cc2088 int imm3) { in Ftmad() argument
2095 ftmad(zd, zd, scratch, imm3); in Ftmad()
2098 ftmad(zd, zd, zm, imm3); in Ftmad()
Dassembler-aarch64.h4489 int imm3);
7287 static Instr ImmSysOp1(int imm3) { in ImmSysOp1() argument
7288 VIXL_ASSERT(IsUint3(imm3)); in ImmSysOp1()
7289 return imm3 << SysOp1_offset; in ImmSysOp1()
7292 static Instr ImmSysOp2(int imm3) { in ImmSysOp2() argument
7293 VIXL_ASSERT(IsUint3(imm3)); in ImmSysOp2()
7294 return imm3 << SysOp2_offset; in ImmSysOp2()
Dassembler-sve-aarch64.cc946 int imm3) { in ftmad() argument
958 ImmUnsignedField<18, 16>(imm3)); in ftmad()
Dmacro-assembler-aarch64.h4721 int imm3);
/external/llvm/lib/Target/Mips/
DMips16InstrFormats.td529 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips16InstrFormats.td528 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DSVEInstrFormats.td1453 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, imm32_0_7:$imm3),
1454 asm, "\t$Zdn, $_Zdn, $Zm, $imm3",
1459 bits<3> imm3;
1463 let Inst{18-16} = imm3;
2901 let Inst{18-16} = imm{2-0}; // imm3
2937 let Inst{18-16} = imm{2-0}; // imm3
2986 let Inst{18-16} = imm{2-0}; // imm3
3096 let Inst{18-16} = imm{2-0}; // imm3
3134 let Inst{18-16} = imm{2-0}; // imm3
3635 let Inst{18-16} = imm{2-0}; // imm3
[all …]
DAArch64InstrFormats.td999 // {2-0} - imm3
/external/capstone/arch/ARM/
DARMMappingInsnOp.inc6421 { /* ARM_tADDi3, ARM_INS_ADD: add${s}${p} $rd, $rm, $imm3 */
6622 { /* ARM_tSUBi3, ARM_INS_SUB: sub${s}${p} $rd, $rm, $imm3 */
/external/capstone/arch/AArch64/
DARMMappingInsnOp.inc6421 { /* ARM_tADDi3, ARM_INS_ADD: add${s}${p} $rd, $rm, $imm3 */
6622 { /* ARM_tSUBi3, ARM_INS_SUB: sub${s}${p} $rd, $rm, $imm3 */
/external/llvm/lib/Target/NVPTX/
DNVPTXIntrinsics.td92 def imm3 : NVPTXInst<
972 def imm3 : NVPTXInst<(outs regclass:$dst),
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc5199 …d:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm3) - Complexity = 7
5200 // Dst: (tADDi3:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm3)
5226 …[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm0_7_neg>><<X:imm_neg_XFORM>>:$imm3) - Complexity = 7
5227 …Dst: (tSUBi3:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm_neg_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm3))
43147 …}:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm3) - Complexity = 7
43148 … // Dst: (tADDSi3:{ *:[i32] }:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm3)
43353 /* 94115*/ OPC_RecordChild1, // #1 = $imm3
43364 …}:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm3) - Complexity = 7
43365 … // Dst: (tSUBSi3:{ *:[i32] }:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm3)
43489 …s:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm3) - Complexity = 7
[all …]
DARMGenMCCodeEmitter.inc6704 // op: imm3
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md8234 int imm3)
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td689 // {2-0} - imm3
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXIntrinsics.td1056 def imm3 : NVPTXInst<(outs regclass:$dst),
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenMCCodeEmitter.inc15009 // op: imm3