| /external/capstone/arch/AArch64/ |
| D | AArch64AddressingModes.h | 131 unsigned immr = (val >> 6) & 0x3f; in AArch64_AM_decodeLogicalImmediate() local
139 unsigned R = immr & (size - 1); in AArch64_AM_decodeLogicalImmediate()
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| D | AArch64InstPrinter.c | 170 int immr = (int)MCOperand_getImm(Op2); in AArch64_printInst() local
173 if (Opcode == AArch64_UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { in AArch64_printInst()
177 ((imms + 1 == immr))) { in AArch64_printInst()
182 shift = immr; in AArch64_printInst()
185 shift = immr; in AArch64_printInst()
188 shift = immr; in AArch64_printInst()
191 shift = immr; in AArch64_printInst()
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| D | AArch64MappingInsnOp.inc | 289 { /* AArch64_BFMWri, ARM64_INS_BFM: bfm $rd, $rn, $immr, $imms */
293 { /* AArch64_BFMXri, ARM64_INS_BFM: bfm $rd, $rn, $immr, $imms */
4909 { /* AArch64_SBFMWri, ARM64_INS_SBFM: sbfm $rd, $rn, $immr, $imms */
4913 { /* AArch64_SBFMXri, ARM64_INS_SBFM: sbfm $rd, $rn, $immr, $imms */
8069 { /* AArch64_UBFMWri, ARM64_INS_UBFM: ubfm $rd, $rn, $immr, $imms */
8073 { /* AArch64_UBFMXri, ARM64_INS_UBFM: ubfm $rd, $rn, $immr, $imms */
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| /external/llvm/test/CodeGen/AArch64/ |
| D | bitfield-insert-0.ll | 3 ; The encoding of lsb -> immr in the CGed bitfield instructions was wrong at one
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 113 int64_t immr = Op2.getImm(); in printInst() local
115 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { in printInst()
119 ((imms + 1 == immr))) { in printInst()
124 shift = immr; in printInst()
127 shift = immr; in printInst()
130 shift = immr; in printInst()
133 shift = immr; in printInst()
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-basic-a64-undefined.txt | 20 # UBFM is undefined when s == 0 and imms<5> or immr<5> is 1.
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64InstPrinter.cpp | 121 int64_t immr = Op2.getImm(); in printInst() local
123 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { in printInst()
127 ((imms + 1 == immr))) { in printInst()
132 shift = immr; in printInst()
135 shift = immr; in printInst()
138 shift = immr; in printInst()
141 shift = immr; in printInst()
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| D | AArch64AddressingModes.h | 296 unsigned immr = (val >> 6) & 0x3f; in decodeLogicalImmediate() local
303 unsigned R = immr & (size - 1); in decodeLogicalImmediate()
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 295 unsigned immr = (val >> 6) & 0x3f; in decodeLogicalImmediate() local
302 unsigned R = immr & (size - 1); in decodeLogicalImmediate()
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| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 740 unsigned immr,
746 unsigned immr,
752 unsigned immr,
7099 static Instr SVEImmRotate(unsigned immr, unsigned lane_size) { in SVEImmRotate() argument
7100 VIXL_ASSERT(IsUintN(WhichPowerOf2(lane_size), immr)); in SVEImmRotate()
7102 return immr << SVEImmRotate_offset; in SVEImmRotate()
7148 static Instr ImmR(unsigned immr, unsigned reg_size) { in ImmR() argument
7149 VIXL_ASSERT(((reg_size == kXRegSize) && IsUint6(immr)) || in ImmR()
7150 ((reg_size == kWRegSize) && IsUint5(immr))); in ImmR()
7152 VIXL_ASSERT(IsUint6(immr)); in ImmR()
[all …]
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| D | assembler-aarch64.cc | 681 unsigned immr, in bfm() argument
685 Emit(SF(rd) | BFM | N | ImmR(immr, rd.GetSizeInBits()) | in bfm()
692 unsigned immr, in sbfm() argument
696 Emit(SF(rd) | SBFM | N | ImmR(immr, rd.GetSizeInBits()) | in sbfm()
703 unsigned immr, in ubfm() argument
707 Emit(SF(rd) | UBFM | N | ImmR(immr, rd.GetSizeInBits()) | in ubfm()
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| D | macro-assembler-aarch64.h | 1109 unsigned immr, in Bfm() argument
1115 bfm(rd, rn, immr, imms); in Bfm()
2286 unsigned immr, in Sbfm() argument
2292 sbfm(rd, rn, immr, imms); in Sbfm()
2578 unsigned immr, in Ubfm() argument
2584 ubfm(rd, rn, immr, imms); in Ubfm()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1643 int immr = SrlImm - ShlImm; in isBitfieldExtractOpFromShr() local
1644 Immr = immr < 0 ? immr + VT.getSizeInBits() : immr; in isBitfieldExtractOpFromShr()
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| D | AArch64InstrFormats.td | 1966 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
1967 asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
1971 bits<6> immr;
1976 let Inst{21-16} = immr;
1986 // imms<5> and immr<5> must be zero, else ReservedValue().
1999 : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
2001 asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
2005 bits<6> immr;
2010 let Inst{21-16} = immr;
2020 // imms<5> and immr<5> must be zero, else ReservedValue().
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1797 int immr = SrlImm - ShlImm; in isBitfieldExtractOpFromShr() local
1798 Immr = immr < 0 ? immr + VT.getSizeInBits() : immr; in isBitfieldExtractOpFromShr()
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| D | AArch64InstrFormats.td | 2542 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
2543 asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
2547 bits<6> immr;
2552 let Inst{21-16} = immr;
2562 // imms<5> and immr<5> must be zero, else ReservedValue().
2575 : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
2577 asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
2581 bits<6> immr;
2586 let Inst{21-16} = immr;
2596 // imms<5> and immr<5> must be zero, else ReservedValue().
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 270 unsigned immr,
2314 unsigned immr,
3111 unsigned immr,
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenMCCodeEmitter.inc | 9888 // op: immr
9911 // op: immr
9989 // op: immr
10011 // op: immr
|