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Searched refs:imull (Results 1 – 25 of 64) sorted by relevance

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/external/llvm/test/MC/X86/AlignedBundling/
Ddifferent-sections.s11 imull $17, %ebx, %ebp
12 imull $17, %ebx, %ebp
14 imull $17, %ebx, %ebp
16 # CHECK-NEXT: 8: imull
20 imull $17, %ebx, %ebp
21 imull $17, %ebx, %ebp
23 imull $17, %ebx, %ebp
25 # CHECK-NEXT: 8: imull
Dswitch-section-locked-error.s10 imull $17, %ebx, %ebp
12 imull $17, %ebx, %ebp
15 imull $17, %ebx, %ebp
Dsingle-inst-bundling.s20 imull $17, %ebx, %ebp
21 # This imull is 3 bytes long and should have started at 0xe, so two bytes
24 # CHECK-NEXT: 10: imull
Dsection-alignment.s14 imull $17, %ebx, %ebp
20 imull $17, %ebx, %ebp
Dalign-mode-argument-error.s7 imull $17, %ebx, %ebp
Dbundle-lock-option-error.s8 imull $17, %ebx, %ebp
/external/llvm/test/CodeGen/X86/
Dmisched-matrix.ll20 ; TOPDOWN: imull {{[0-9]*}}(
22 ; TOPDOWN: imull {{[0-9]*}}(
28 ; scheduled independently, and that the imull/adds are interleaved.
32 ; ILPMIN: imull
33 ; ILPMIN: imull
35 ; ILPMIN: imull
37 ; ILPMIN: imull
40 ; ILPMIN: imull
41 ; ILPMIN: imull
43 ; ILPMIN: imull
[all …]
Dmisched-balance.ll12 ; imull folded loads should be in order and interleaved with addl, never
20 ; CHECK: imull 4
21 ; CHECK-NOT: {{imull|rsp}}
23 ; CHECK: imull 8
24 ; CHECK-NOT: {{imull|rsp}}
26 ; CHECK: imull 12
27 ; CHECK-NOT: {{imull|rsp}}
29 ; CHECK: imull 16
30 ; CHECK-NOT: {{imull|rsp}}
32 ; CHECK: imull 20
[all …]
Datom-sched.ll14 ; atom: imull
16 ; atom: imull
17 ; slm: imull
19 ; slm: imull
20 ; CHECK: imull
22 ; CHECK: imull
Dvector-idiv-udiv-512.ll309 ; AVX512BW-NEXT: imull $37, %eax, %ecx
317 ; AVX512BW-NEXT: imull $37, %ecx, %edx
327 ; AVX512BW-NEXT: imull $37, %eax, %ecx
336 ; AVX512BW-NEXT: imull $37, %eax, %ecx
345 ; AVX512BW-NEXT: imull $37, %eax, %ecx
354 ; AVX512BW-NEXT: imull $37, %eax, %ecx
363 ; AVX512BW-NEXT: imull $37, %eax, %ecx
372 ; AVX512BW-NEXT: imull $37, %eax, %ecx
381 ; AVX512BW-NEXT: imull $37, %eax, %ecx
390 ; AVX512BW-NEXT: imull $37, %eax, %ecx
[all …]
Dvector-idiv-sdiv-512.ll336 ; AVX512BW-NEXT: imull $-109, %eax, %ecx
346 ; AVX512BW-NEXT: imull $-109, %ecx, %edx
358 ; AVX512BW-NEXT: imull $-109, %eax, %ecx
369 ; AVX512BW-NEXT: imull $-109, %eax, %ecx
380 ; AVX512BW-NEXT: imull $-109, %eax, %ecx
391 ; AVX512BW-NEXT: imull $-109, %eax, %ecx
402 ; AVX512BW-NEXT: imull $-109, %eax, %ecx
413 ; AVX512BW-NEXT: imull $-109, %eax, %ecx
424 ; AVX512BW-NEXT: imull $-109, %eax, %ecx
435 ; AVX512BW-NEXT: imull $-109, %eax, %ecx
[all …]
Ddivide-by-constant.ll10 ; CHECK: imull $63551, %eax
21 ; CHECK: imull $43691, %eax
33 ; CHECK-NEXT: imull $171, %eax
44 ; CHECK: imull $1986, %eax
60 ; CHECK: imull $26215, %eax
83 ; CHECK: imull $211
93 ; CHECK: imull $71
Dsdiv-exact.ll7 ; CHECK: imull $-1030792151, 4(%esp)
16 ; CHECK-NEXT: imull $-1431655765
Dimul.ll73 ; X86: imull
83 ; X86-NEXT: imull
123 ; X64: imull
125 ; X86: imull
Dmul64.ll13 ; X32-NEXT: imull {{[0-9]+}}(%esp), %ecx
15 ; X32-NEXT: imull {{[0-9]+}}(%esp), %esi
D2010-09-01-RemoveCopyByCommutingDef.ll13 ; The imull clobbers a 32-bit register.
14 ; CHECK: imull %{{...}}, %e[[CLOBBER:..]]
Dsink-blockfreq.ll13 ; MSINK_BFI-NEXT: imull
16 ; MSINK_NOBFI: imull
Dmemset-2.ll39 ; CHECK-NEXT: imull $16843009, %ecx, %ecx ## imm = 0x1010101
54 ; CHECK-NEXT: imull $16843009, %ecx, %ecx ## imm = 0x1010101
Dmachine-combiner-int.ll16 ; CHECK-NEXT: imull %ecx, %edx
17 ; CHECK-NEXT: imull %edx, %eax
32 ; CHECK-NEXT: imull %ecx, %edx
33 ; CHECK-NEXT: imull %edx, %eax
/external/compiler-rt/lib/builtins/i386/
Dmuldi3.S16 imull %eax, %ecx // b.lo * a.hi
20 imull %edx, %ebx // a.lo * b.hi
Dudivdi3.S59 imull %edi, %eax // q*bhi
91 imull %edi, %eax // q*bhi
Dumoddi3.S60 imull %edi, %eax // q*bhi
96 imull %edi, %eax // q*bhi
Ddivdi3.S88 imull %edi, %eax // q*bhi
126 imull %edi, %eax // q*bhi
Dmoddi3.S87 imull %edi, %eax // q*bhi
127 imull %edi, %eax // q*bhi
/external/llvm/test/Instrumentation/AddressSanitizer/X86/
Dbug_11395.ll63 …imull 0x1c+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A…

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