| /external/arm-optimized-routines/string/aarch64/ |
| D | strlen-sve.S | 38 incp x1, p0.b
49 incp x1, p0.b
|
| D | memchr-sve.S | 44 incp x0, p2.b /* form final pointer to c */
54 incp x3, p0.b
|
| D | strcpy-sve.S | 55 incp x2, p0.b
64 incp x0, p0.b
|
| D | strnlen-sve.S | 54 incp x0, p2.b
64 incp x2, p1.b
|
| D | strchr-sve.S | 48 incp x0, p4.b
64 incp x0, p0.b
|
| D | strcmp-sve.S | 48 2: incp x2, p0.b /* skip bytes for next round */
|
| D | strncmp-sve.S | 59 incp x3, p1.b
|
| D | strrchr-sve.S | 51 incp x0, p0.b /* skip bytes this round */
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12512 "inch\004incp\004incw\005index\003ins\004insr\003irg\003isb\005lasta\005"
14702 …{ 1809 /* incp */, AArch64::INCP_XP_H, Convert__Reg1_0__SVEPredicateHReg1_1__Tie0_1_1, AMFBS_HasSV…
14703 …{ 1809 /* incp */, AArch64::INCP_XP_S, Convert__Reg1_0__SVEPredicateSReg1_1__Tie0_1_1, AMFBS_HasSV…
14704 …{ 1809 /* incp */, AArch64::INCP_XP_D, Convert__Reg1_0__SVEPredicateDReg1_1__Tie0_1_1, AMFBS_HasSV…
14705 …{ 1809 /* incp */, AArch64::INCP_XP_B, Convert__Reg1_0__SVEPredicateBReg1_1__Tie0_1_1, AMFBS_HasSV…
14706 …{ 1809 /* incp */, AArch64::INCP_ZP_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicateHReg1_1, A…
14707 …{ 1809 /* incp */, AArch64::INCP_ZP_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1,…
14708 …{ 1809 /* incp */, AArch64::INCP_ZP_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicateSReg1_1, A…
14709 …{ 1809 /* incp */, AArch64::INCP_ZP_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1,…
14710 …{ 1809 /* incp */, AArch64::INCP_ZP_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicateDReg1_1, A…
[all …]
|
| /external/vixl/test/aarch64/ |
| D | test-disasm-sve-aarch64.cc | 2023 COMPARE(incp(x26, p8.VnB()), "incp x26, p8.b"); in TEST()
2024 COMPARE(incp(x26, p8.VnH()), "incp x26, p8.h"); in TEST()
2025 COMPARE(incp(x26, p8.VnS()), "incp x26, p8.s"); in TEST()
2026 COMPARE(incp(x26, p8.VnD()), "incp x26, p8.d"); in TEST()
2027 COMPARE(incp(z27.VnH(), p9), "incp z27.h, p9"); in TEST()
2028 COMPARE(incp(z27.VnS(), p9), "incp z27.s, p9"); in TEST()
2029 COMPARE(incp(z27.VnD(), p9), "incp z27.d, p9"); in TEST()
|
| D | test-api-movprfx-aarch64.cc | 1137 __ incp(z9.VnD(), p1); in TEST() local
1434 __ incp(z14.VnD(), p1); in TEST() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SVEInstrInfo.td | 921 defm INCP_XP : sve_int_count_r_x64<0b10000, "incp">;
928 defm INCP_ZP : sve_int_count_v<0b10000, "incp">;
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 4513 void incp(const Register& rdn, const PRegisterWithLaneSize& pg);
4516 void incp(const ZRegister& zdn, const PRegister& pg);
|
| D | assembler-sve-aarch64.cc | 2047 void Assembler::incp(const Register& rdn, const PRegisterWithLaneSize& pg) { in incp() function in vixl::aarch64::Assembler
2059 void Assembler::incp(const ZRegister& zdn, const PRegister& pg) { in incp() function in vixl::aarch64::Assembler
|
| D | macro-assembler-aarch64.h | 4760 incp(rdn, pg); in Incp()
4767 incp(zd, pg); in Incp()
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 8311 void incp(const Register& rdn, const PRegisterWithLaneSize& pg)
8318 void incp(const ZRegister& zdn, const PRegister& pg)
|