| /external/llvm/test/CodeGen/X86/ |
| D | lsr-sort.ll | 3 ; RUN: not grep incw %t
|
| D | atomic_add.ll | 71 ; CHECK: incw
73 ; SLOW_INC-NOT: incw
|
| D | atomic16.ll | 13 ; X64: incw
15 ; X32: incw
|
| D | rd-mod-wr-eflags.ll | 151 ; CHECK: incw {{[0-9][0-9]*}}({{.*}})
|
| D | atomic_mi.ll | 702 ; X64-NOT: incw
704 ; X32-NOT: incw
706 ; SLOW_INC-NOT: incw
|
| D | xaluo.ll | 72 ; CHECK: incw %di
214 ; CHECK-NOT: incw %di
|
| /external/llvm/test/MC/X86/ |
| D | x86-16.s | 544 incw %ax
|
| D | x86-32.s | 683 incw %ax
|
| D | x86-64.s | 1034 incw %ax // CHECK: incw %ax # encoding: [0x66,0xff,0xc0] label
|
| D | x86-32-coverage.s | 389 incw 0x7eed
|
| /external/llvm/test/MC/Disassembler/X86/ |
| D | x86-16.txt | 501 # CHECK: incw %ax
|
| D | x86-64.txt | 212 # CHECK: incw %cx
|
| D | x86-32.txt | 706 # CHECK: incw %cx
|
| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 458 #define INC_W(a) CHOICE(incw a, incw a, _WTOG inc a)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SVEInstrInfo.td | 853 defm INCW_XPiI : sve_int_pred_pattern_a<0b100, "incw">;
904 defm INCW_ZPiI : sve_int_countvlv<0b10100, "incw", ZPR32>;
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 4519 void incw(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
4522 void incw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
|
| D | assembler-sve-aarch64.cc | 454 V(incw, INCW_r_rs) \
523 V(incw, INC, W) \
|
| D | macro-assembler-aarch64.h | 4773 incw(rdn, pattern, multiplier);
4778 incw(zdn, pattern, multiplier);
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12512 "inch\004incp\004incw\005index\003ins\004insr\003irg\003isb\005lasta\005"
14712 …{ 1814 /* incw */, AArch64::INCW_XPiI, Convert__Reg1_0__Tie0_1_1__imm_95_31__imm_95_1, AMFBS_HasSV…
14713 …{ 1814 /* incw */, AArch64::INCW_ZPiI, Convert__SVEVectorSReg1_0__Tie0_1_1__imm_95_31__imm_95_1, A…
14714 …{ 1814 /* incw */, AArch64::INCW_XPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1, AMFBS_H…
14715 …{ 1814 /* incw */, AArch64::INCW_ZPiI, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPattern1_1__imm_95_…
14716 …{ 1814 /* incw */, AArch64::INCW_XPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161_3, AMFBS…
14717 …{ 1814 /* incw */, AArch64::INCW_ZPiI, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPattern1_1__Imm1_16…
22085 …{ 1814 /* incw */, AArch64::INCW_XPiI, Convert__Reg1_0__Tie0_1_1__imm_95_31__imm_95_1, AMFBS_HasSV…
22086 …{ 1814 /* incw */, AArch64::INCW_ZPiI, Convert__SVEVectorSReg1_0__Tie0_1_1__imm_95_31__imm_95_1, A…
22087 …{ 1814 /* incw */, AArch64::INCW_XPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1, AMFBS_H…
[all …]
|
| D | AArch64GenAsmWriter.inc | 22261 /* 2542 */ "incw $\x01\0"
22262 /* 2550 */ "incw $\x01, $\xFF\x03\x0E\0"
22263 /* 2564 */ "incw $\xFF\x01\x0B\0"
22264 /* 2574 */ "incw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
|
| D | AArch64GenAsmWriter1.inc | 22982 /* 2542 */ "incw $\x01\0"
22983 /* 2550 */ "incw $\x01, $\xFF\x03\x0E\0"
22984 /* 2564 */ "incw $\xFF\x01\x0B\0"
22985 /* 2574 */ "incw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
|
| /external/vixl/test/aarch64/ |
| D | test-api-movprfx-aarch64.cc | 1140 __ incw(z30.VnS(), SVE_ALL); in TEST() local
1437 __ incw(z26.VnS(), SVE_ALL); in TEST() local
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 8325 void incw(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1)
8332 void incw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1)
|
| /external/elfutils/tests/ |
| D | testfile44.expect.bz2 | 1testfile44.o: elf32-elf_i386
2
3Disassembly of section .text:
4
5 0 ... |
| D | testfile45.expect.bz2 | 1testfile45.o: elf64-elf_x86_64
2
3Disassembly of section .text:
4
5 0 ... |