| /external/llvm/lib/CodeGen/ |
| D | ProcessImplicitDefs.cpp | 72 if (MO.isReg() && MO.isUse() && MO.readsReg()) in canTurnIntoImplicitDef()
112 if (MO.isUse()) in processImplicitDef()
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| D | ExpandPostRAPseudos.cpp | 74 if (!MO.isReg() || !MO.isImplicit() || MO.isUse()) in TransferImplicitDefs()
84 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && in LowerSubregToReg()
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| D | MachineInstr.cpp | 350 if (isUndef() && isUse()) { in print()
848 if (NewMO->isUse()) { in addOperand()
1194 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
1278 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg) in hasRegisterImplicitUseOperand()
1291 if (!MO.isReg() || !MO.isUse()) in findRegisterUseOperandIdx()
1323 if (MO.isUse()) in readsWritesVirtualRegister()
1403 assert(UseMO.isUse() && "UseIdx must be a use operand"); in tieOperands()
1435 if (MO.isUse()) in findTiedOperandIdx()
1440 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) in findTiedOperandIdx()
1483 if (MO.isReg() && MO.isUse()) in clearKillInfo()
[all …]
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| D | TwoAddressInstructionPass.cpp | 208 if (MO.isUse() && MOReg != SavedReg) in sink3AddrInstruction()
367 if (MO.isUse() && DI->second < LastUse) in noUseAfterLastDef()
478 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse()
1053 if (MO.isUse()) { in rescheduleKillAboveMI()
1092 if (MO.isUse()) { in rescheduleKillAboveMI()
1342 if (MO.isUse()) { in tryInstructionTransform()
1421 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid"); in collectTiedOperands()
1534 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() && in processTiedPairs()
1560 MO.isUse()) { in processTiedPairs()
1596 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { in processTiedPairs()
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| D | RegAllocFast.cpp | 240 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) { in addKillFlag()
620 if (LRI->LastUse != &MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse()) in defineVirtReg()
653 if (MO.isUse()) in reloadVirtReg()
753 if (MO.isUse()) { in handleThroughOperands()
942 if (MO.isUse()) { in AllocateBasicBlock()
954 if (MO.isUse()) { in AllocateBasicBlock()
990 if (MO.isUse()) { in AllocateBasicBlock()
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| D | MachineSink.cpp | 377 if (!MO.isReg() || !MO.isUse()) in isWorthBreakingCriticalEdge()
603 if (MO.isUse()) { in FindSuccToSinkTo()
615 if (MO.isUse()) continue; in FindSuccToSinkTo()
852 if (MO.isReg() && MO.isUse()) in SinkInstruction()
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| D | RegisterScavenging.cpp | 128 if (MO.isUse()) { in determineKillsAndDefs()
198 if (MO.isUse()) { in forward()
359 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) && in scavengeRegister()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ProcessImplicitDefs.cpp | 70 if (MO.isReg() && MO.isUse() && MO.readsReg()) in canTurnIntoImplicitDef()
110 if (MO.isUse()) in processImplicitDef()
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| D | RegAllocFast.cpp | 372 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) { in addKillFlag()
797 if (LRI->LastUse != &MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse()) in defineVirtReg()
824 if (MO.isUse()) in reloadVirtReg()
896 if (MO.isEarlyClobber() || (MO.isUse() && MO.isTied()) || in handleThroughOperands()
926 if (MO.isUse()) { in handleThroughOperands()
1051 if (MO.isUse()) { in allocateInstruction()
1063 if (MO.isUse()) { in allocateInstruction()
1101 if (MO.isUse()) { in allocateInstruction()
1125 if (!MO.isReg() || !MO.isUse()) in allocateInstruction()
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| D | ReachingDefAnalysis.cpp | 109 if (MO.isUse()) in processDefs()
238 if (!MO.isReg() || !MO.isUse() || MO.getReg() != PhysReg) in getReachingLocalUses()
317 if (MO.isReg() && MO.isUse() && MO.getReg() == PhysReg) in getInstWithUseBefore()
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| D | TwoAddressInstructionPass.cpp | 236 if (MO.isUse() && MOReg != SavedReg) in sink3AddrInstruction()
395 if (MO.isUse() && DI->second < LastUse) in noUseAfterLastDef()
505 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse()
1096 if (MO.isUse()) { in rescheduleKillAboveMI()
1135 if (MO.isUse()) { in rescheduleKillAboveMI()
1401 if (MO.isUse()) { in tryInstructionTransform()
1480 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid"); in collectTiedOperands()
1592 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() && in processTiedPairs()
1617 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { in processTiedPairs()
1657 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { in processTiedPairs()
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| D | MachineInstr.cpp | 280 if (NewMO->isUse()) { in addOperand()
847 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
934 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg) in hasRegisterImplicitUseOperand()
947 if (!MO.isReg() || !MO.isUse()) in findRegisterUseOperandIdx()
975 if (MO.isUse()) in readsWritesVirtualRegister()
1054 assert(UseMO.isUse() && "UseIdx must be a use operand"); in tieOperands()
1086 if (MO.isUse()) in findTiedOperandIdx()
1091 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) in findTiedOperandIdx()
1134 if (MO.isReg() && MO.isUse()) in clearKillInfo()
1388 if (!MO.isReg() || MO.isUse()) in allDefsAreDead()
[all …]
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| D | LiveIntervals.cpp | 792 if (MO.isUse()) { in addKillFlags()
864 float LiveIntervals::getSpillWeight(bool isDef, bool isUse, in getSpillWeight() argument
867 return getSpillWeight(isDef, isUse, MBFI, MI.getParent()); in getSpillWeight()
870 float LiveIntervals::getSpillWeight(bool isDef, bool isUse, in getSpillWeight() argument
875 return (isDef + isUse) * (Freq.getFrequency() * Scale); in getSpillWeight()
992 if (MO.isUse()) { in updateAllRanges()
1076 if (MOP.isReg() && MOP.isUse()) in handleMoveDown()
1377 if (MO->isReg() && !MO->isUse()) in handleMoveUp()
1573 } else if (MO.isUse()) { in repairOldRegInRange()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | DelaySlotFiller.cpp | 263 if (MO.isUse()) { in delayHasHazard()
304 assert(Reg.isUse() && "CALL first operand is not a use."); in insertCallDefsUses()
311 assert(Operand1.isUse() && "CALLrr second operand is not a use."); in insertCallDefsUses()
332 if (MO.isUse()) { in insertDefsUses()
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| /external/llvm/lib/Target/Sparc/ |
| D | DelaySlotFiller.cpp | 266 if (MO.isUse()) { in delayHasHazard()
307 assert(Reg.isUse() && "CALL first operand is not a use."); in insertCallDefsUses()
314 assert(Operand1.isUse() && "CALLrr second operand is not a use."); in insertCallDefsUses()
335 if (MO.isUse()) { in insertDefsUses()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 839 if ((!ReturnUses && op->isUse()) || in defusechain_iterator()
854 if (Op->isUse()) in advance()
941 if ((!ReturnUses && op->isUse()) || in defusechain_instr_iterator()
956 if (Op->isUse()) in advance()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiDelaySlotFiller.cpp | 215 if (MO.isUse()) { in delayHasHazard()
241 else if (MO.isUse()) in insertDefsUses()
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiDelaySlotFiller.cpp | 217 if (MO.isUse()) { in delayHasHazard()
243 else if (MO.isUse()) in insertDefsUses()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | Utils.cpp | 56 if (RegMO.isUse()) { in constrainOperandRegClass()
92 assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) && in constrainOperandRegClass()
149 if (MO.isUse()) { in constrainSelectedInstRegOperands()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInsertWaits.cpp | 268 if (I->isReg() && I->isUse()) in isOpRelevant()
350 if (Op.isUse()) in pushInstruction()
480 if (Op.isUse()) in handleOperands()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonNewValueJump.cpp | 154 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { in INITIALIZE_PASS_DEPENDENCY()
607 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
614 if (localMO.isReg() && localMO.isUse() && in runOnMachineFunction()
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| D | HexagonGenPredicate.cpp | 238 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse()); in getPredRegFor()
334 if (Mo->isReg() && Mo->isUse()) in isScalarPred()
356 if (!MO.isReg() || !MO.isUse()) in convertToPredForm()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 980 if ((!ReturnUses && op->isUse()) || in defusechain_iterator()
994 if (Op->isUse()) in advance()
1086 if ((!ReturnUses && op->isUse()) || in defusechain_instr_iterator()
1100 if (Op->isUse()) in advance()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonGenPredicate.cpp | 259 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse()); in getPredRegFor()
355 if (MO.isReg() && MO.isUse()) in isScalarPred()
376 if (!MO.isReg() || !MO.isUse()) in convertToPredForm()
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| D | HexagonNewValueJump.cpp | 178 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { in INITIALIZE_PASS_DEPENDENCY()
653 if (!MO.isReg() || !MO.isUse()) in runOnMachineFunction()
660 if (!Op.isReg() || !Op.isUse() || !Op.isKill()) in runOnMachineFunction()
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