Searched refs:kFormatVnD (Results 1 – 7 of 7) sorted by relevance
/external/vixl/src/aarch64/ |
D | instructions-aarch64.cc | 318 ((movprfx_vform == kFormatVnD) && pg_matches_low8)) && in CanTakeSVEMovprfx() 563 case kFormatVnD: in GetSVEMulZmAndIndex() 595 case kFormatVnD: in GetSVEMulLongZmAndIndex() 1023 case kFormatVnD: in VectorFormatHalfWidth() 1051 return kFormatVnD; in VectorFormatDoubleWidth() 1101 case kFormatVnD: in VectorFormatHalfWidthDoubleLanes() 1163 case kFormatVnD: in IsSVEFormat() 1182 return kFormatVnD; in SVEFormatFromLaneSizeInBytes() 1283 case kFormatVnD: in LaneSizeInBitsFromFormat() 1323 case kFormatVnD: in LaneSizeInBytesLog2FromFormat()
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D | simulator-aarch64.cc | 1116 case kFormatVnD: in GetPrintRegisterFormat() 2269 fcvt(kFormatVnS, kFormatVnD, result, pg, zn); in Simulate_ZdS_PgM_ZnD() 2284 mov_merging(kFormatVnD, zd, pg, result); in Simulate_ZdS_PgM_ZnD() 2300 fcvt(kFormatVnD, kFormatVnS, zd, pg, result); in SimulateSVEFPConvertLong() 2364 if ((vform == kFormatVnS) || (vform == kFormatVnD)) { in Simulate_ZdT_PgZ_ZnT_ZmT() 2392 SVEBitwiseLogicalUnpredicatedHelper(EOR, kFormatVnD, result, zn, result); in Simulate_ZdT_ZnT_ZmT() 2397 SVEBitwiseLogicalUnpredicatedHelper(EOR, kFormatVnD, result, zn, result); in Simulate_ZdT_ZnT_ZmT() 2840 vform = kFormatVnD; in SimulateSVESaturatingMulAddHigh() 2875 sqdmlal(kFormatVnD, zda, zn_b, zm_idx); in Simulate_ZdaD_ZnS_ZmS_imm() 2878 sqdmlal(kFormatVnD, zda, zn_t, zm_idx); in Simulate_ZdaD_ZnS_ZmS_imm() [all …]
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D | instructions-aarch64.h | 212 kFormatVnD = SVE_D | kFormatSVE, enumerator 331 return kFormatVnD;
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D | logic-aarch64.cc | 638 VIXL_ASSERT((vform == kFormatVnS) || (vform == kFormatVnD)); in sdiv() 643 int64_t min_int = (vform == kFormatVnD) ? kXMinInt : kWMinInt; in sdiv() 660 VIXL_ASSERT((vform == kFormatVnS) || (vform == kFormatVnD)); in udiv() 2888 d[i] = src.Uint(kFormatVnD, (src_index * count) + i); in dup_element() 2892 dst.SetUint(kFormatVnD, i, d[i % count]); in dup_element() 4168 if (vform == kFormatVnD) { in sqrdmlash() 6489 case kFormatVnD: in flogb() 6999 op2 = is_wide_elements ? src2.Int(kFormatVnD, d_lane) in SVEIntCompareVectorsHelper() 7007 op2 = is_wide_elements ? src2.Uint(kFormatVnD, d_lane) in SVEIntCompareVectorsHelper() 7064 VectorFormat shift_vform = is_wide_elements ? kFormatVnD : vform; in SVEBitwiseShiftHelper() [all …]
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D | disasm-aarch64.cc | 5489 if ((vform == kFormatVnS) || (vform == kFormatVnD)) { in Disassemble_PdT_PgZ_ZnT_ZmT() 5591 if ((vform == kFormatVnS) || (vform == kFormatVnD)) { in Disassemble_ZdT_PgZ_ZnT_ZmT()
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/external/vixl/test/aarch64/ |
D | test-api-aarch64.cc | 299 VIXL_CHECK(ZRegister(3, kFormatVnD).Is(z3.VnD())); in TEST() 314 VIXL_CHECK(PRegisterWithLaneSize(3, kFormatVnD).Is(p3.VnD())); in TEST() 1555 temps.Include(ZRegister(3, kFormatVnD)); in TEST() 1587 temps.Exclude(ZRegister(3, kFormatVnD)); in TEST() 1619 temps.Release(ZRegister(3, kFormatVnD)); in TEST() 1639 temps.Include(PRegisterWithLaneSize(2, kFormatVnD)); in TEST() 1671 temps.Exclude(PRegisterWithLaneSize(2, kFormatVnD)); in TEST() 1703 temps.Release(PRegisterWithLaneSize(2, kFormatVnD)); in TEST()
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D | test-trace-aarch64.cc | 3065 reg.SetUint(kFormatVnD, lane, base | mantissas); in TraceTestHelper()
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