| /external/vixl/test/aarch64/ |
| D | test-assembler-sve-aarch64.cc | 478 TEST_SVE(sve_mla_mls_h) { MlaMlsHelper(config, kHRegSize); } in TEST_SVE()
1558 ASSERT_EQUAL_64(0x4000000000000000 + core.GetSVELaneCount(kHRegSize), x21); in TEST_SVE()
1669 ASSERT_EQUAL_64(core.GetSVELaneCount(kHRegSize), x22); in TEST_SVE()
1778 ASSERT_EQUAL_64(0x4000000000000000 + core.GetSVELaneCount(kHRegSize), x21); in TEST_SVE()
1913 int h_lane_count = core.GetSVELaneCount(kHRegSize); in TEST_SVE()
2061 int h_lane_count = core.GetSVELaneCount(kHRegSize); in TEST_SVE()
2221 int h_lane_count = core.GetSVELaneCount(kHRegSize); in TEST_SVE()
2278 int h_lane_count = core.GetSVELaneCount(kHRegSize); in TEST_SVE()
2283 uint64_t h_mask = GetUintMask(kHRegSize); in TEST_SVE()
3130 PnextHelper(config, kHRegSize, in0, in0, exp00); in TEST_SVE()
[all …]
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| D | test-api-aarch64.cc | 247 VIXL_CHECK(VRegister(1, kHRegSize).Is(h1)); in TEST()
254 VIXL_CHECK(VRegister(1, kHRegSize, 1).Is(h1)); in TEST()
291 VIXL_CHECK(ZRegister(1, kHRegSize).Is(z1.VnH())); in TEST()
306 VIXL_CHECK(PRegisterWithLaneSize(1, kHRegSize).Is(p1.VnH())); in TEST()
327 VIXL_CHECK(CPURegister(3, kHRegSize, CPURegister::kVRegister).Is(h3)); in TEST()
580 VIXL_CHECK(p14.VnH().GetLaneSizeInBits() == kHRegSize); in TEST()
1561 temps.Include(ZRegister(12), ZRegister(13, kHRegSize), z14); in TEST()
1593 temps.Exclude(ZRegister(12), ZRegister(13, kHRegSize), z14); in TEST()
1646 temps.Include(PRegister(11), PRegisterWithLaneSize(12, kHRegSize)); in TEST()
1678 temps.Exclude(PRegister(11), PRegisterWithLaneSize(12, kHRegSize)); in TEST()
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| D | test-utils-aarch64.cc | 737 case kHRegSize: in GetSignallingNan()
796 case kHRegSize: in SetFpData()
876 SetFpData(masm, kHRegSize, kInputFloat16Basic, lcg_mult); in InitialiseRegisterFp()
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| D | test-utils-aarch64.h | 177 case kHRegSize: in zreg_lane()
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| D | test-simulator-aarch64.cc | 243 (d_size == kHRegSize)); in Test1Op_Helper()
245 (n_size == kHRegSize)); in Test1Op_Helper()
388 (reg_size == kHRegSize)); in Test2Op_Helper()
545 (reg_size == kHRegSize)); in Test3Op_Helper()
974 (n_size == kHRegSize)); in TestFPToFixed_Helper()
1040 (n_size == kHRegSize)); in TestFPToInt_Helper()
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| /external/vixl/benchmarks/aarch64/ |
| D | bench-utils.cc | 92 if (entropy == 0) return kHRegSize; in PickFPSize()
363 if (other_size < kHRegSize) other_size = kDRegSize; in GenerateFPSequence()
364 if (other_size > kDRegSize) other_size = kHRegSize; in GenerateFPSequence()
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| D | bench-utils.h | 238 vixl::aarch64::VRegister PickH() { return PickV(vixl::aarch64::kHRegSize); } in PickH()
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| /external/vixl/src/aarch64/ |
| D | registers-aarch64.h | 441 case kHRegSize: in EncodeSizeInBits()
613 ZRegister VnH() const { return ZRegister(GetCode(), kHRegSize); } in VnH()
744 return PRegisterWithLaneSize(GetCode(), kHRegSize); in VnH()
773 V(HRegister, kHRegSize, VRegister) \
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| D | logic-aarch64.cc | 2538 case kHRegSize: in fadda()
2595 if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { in fcadd()
2674 if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { in fcmla()
2691 if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { in fcmla()
5001 if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { \
5045 if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { in frecps()
5077 if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { in frsqrts()
5146 if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { in fcmp()
5163 if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { in fcmp_zero()
5185 if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { in fabscmp()
[all …]
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| D | instructions-aarch64.h | 55 const unsigned kHRegSize = 16; variable
57 const unsigned kHRegSizeInBytes = kHRegSize / 8;
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| D | instructions-aarch64.cc | 38 VIXL_ASSERT((reg_size == kBRegSize) || (reg_size == kHRegSize) || in RepeatBitsAcrossReg()
1234 return kHRegSize; in RegisterSizeInBitsFromFormat()
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| D | macro-assembler-sve-aarch64.cc | 387 if (zd.GetLaneSizeInBits() >= kHRegSize) { in Cpy()
390 case kHRegSize: in Cpy()
827 case kHRegSize: in Fdup()
848 case kHRegSize: in Fdup()
869 case kHRegSize: in Fdup()
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| D | simulator-aarch64.cc | 893 VIXL_ASSERT((reg_size == kBRegSize) || (reg_size == kHRegSize) || in ShiftOperand()
1384 case kHRegSize: in PrintVRegister()
10439 dst_data_size = kHRegSize; in VisitSVEFPConvertToInt()
10440 src_data_size = kHRegSize; in VisitSVEFPConvertToInt()
10445 src_data_size = kHRegSize; in VisitSVEFPConvertToInt()
10450 src_data_size = kHRegSize; in VisitSVEFPConvertToInt()
10592 dst_data_size = kHRegSize; in VisitSVEIntConvertToFP()
10593 src_data_size = kHRegSize; in VisitSVEIntConvertToFP()
10602 dst_data_size = kHRegSize; in VisitSVEIntConvertToFP()
10617 dst_data_size = kHRegSize; in VisitSVEIntConvertToFP()
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| D | assembler-sve-aarch64.cc | 4508 case kHRegSize: in SVEGatherPrefetchVectorPlusImmediateHelper()
4543 case kHRegSize: in SVEGatherPrefetchScalarPlusImmediateHelper()
4574 case kHRegSize: in SVEContiguousPrefetchScalarPlusScalarHelper()
4614 case kHRegSize: in SVEContiguousPrefetchScalarPlusVectorHelper()
4638 case kHRegSize: in SVEContiguousPrefetchScalarPlusVectorHelper()
4663 case kHRegSize: in SVEContiguousPrefetchScalarPlusVectorHelper()
4736 SVEPrefetchHelper(prfop, pg, addr, kHRegSize); in prfh()
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| D | disasm-aarch64.cc | 5888 case kHRegSize: in AppendRegisterNameToOutput()
6242 reg_size = kHRegSize; in SubstituteRegisterField()
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| D | assembler-aarch64.cc | 5982 VIXL_ASSERT((width == kBRegSize) || (width == kHRegSize) || in IsImmLogical()
6188 case kHRegSize: in LoadOpFor()
6211 case kHRegSize: in StoreOpFor()
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