Searched refs:kQRegSizeInBytes (Results 1 – 12 of 12) sorted by relevance
| /external/vixl/test/aarch64/ |
| D | test-utils-aarch64.h | 88 typedef VectorValue<kQRegSizeInBytes> QRegisterValue;
104 VIXL_ASSERT(sizeof(dump_.q_[0]) == kQRegSizeInBytes); in RegisterDump()
282 memcmp(&dump_.q_[code], &dump_.z_[code], kQRegSizeInBytes) == 0; in VRegAliasesMatch()
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| D | test-utils-aarch64.cc | 683 DumpRegisters<VRegister>(masm, dump_base, q_offset, kQRegSizeInBytes); in Dump()
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| D | test-assembler-sve-aarch64.cc | 296 uint8_t data[kQRegSizeInBytes]; in TEST_SVE()
297 for (size_t i = 0; i < kQRegSizeInBytes; i++) { in TEST_SVE()
356 for (int i = kQRegSizeInBytes; i < core.GetSVELaneCount(kBRegSize); i++) { in TEST_SVE()
9367 __ Mov(x0, data + page_size - (kQRegSizeInBytes / kBRegSizeInBytes) / 2); in TEST_SVE()
9411 __ Mov(x0, data + page_size - (kQRegSizeInBytes / kSRegSizeInBytes) / 2); in TEST_SVE()
9419 __ Mov(x0, data + page_size - (kQRegSizeInBytes / kHRegSizeInBytes) / 2); in TEST_SVE()
9551 if (loaded_data_in_bytes < kQRegSizeInBytes) { in TEST_SVE()
10457 int data_size = (kQRegSizeInBytes + 128) * 2; in TEST_SVE()
19858 int data_size = (kQRegSizeInBytes + 128) * 4; in Testsve_ld1ro()
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| D | test-simulator-aarch64.cc | 1724 __ Str(vdstr, MemOperand(out, kQRegSizeInBytes, PostIndex)); in Test1OpAcrossNEON_Helper()
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| D | test-assembler-aarch64.cc | 11276 offset += 2 * kQRegSizeInBytes; in TEST()
11493 preindex = 2 * kQRegSizeInBytes; in TEST()
11662 postindex = 2 * kQRegSizeInBytes; in TEST()
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| /external/vixl/src/aarch32/ |
| D | constants-aarch32.h | 55 const unsigned kQRegSizeInBytes = kQRegSizeInBits / 8; variable
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| /external/vixl/src/aarch64/ |
| D | instructions-aarch64.h | 77 const unsigned kQRegSizeInBytes = kQRegSize / 8; variable
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| D | simulator-aarch64.h | 1499 uint8_t val[kQRegSizeInBytes];
1513 (sizeof(T) == kQRegSizeInBytes));
1622 (sizeof(value) == kQRegSizeInBytes) ||
2428 int reg_size_in_bytes = kQRegSizeInBytes);
2440 kQRegSizeInBytes),
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| D | assembler-aarch64.h | 199 (size_ == kQRegSizeInBytes)); in GetSize()
205 VIXL_ASSERT(size_ == kQRegSizeInBytes); in GetRawValue128Low64()
213 VIXL_ASSERT(size_ == kQRegSizeInBytes); in GetRawValue128High64()
306 : RawLiteral(kQRegSizeInBytes, literal_pool, ownership) { in RawLiteral() argument
307 VIXL_STATIC_ASSERT(sizeof(low64) == (kQRegSizeInBytes / 2)); in RawLiteral()
355 VIXL_ASSERT(GetSize() == kQRegSizeInBytes); in RewriteValueInCode()
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| D | simulator-aarch64.cc | 1039 case kQRegSizeInBytes: in GetPrintRegisterFormatForSize()
1052 case kQRegSizeInBytes: in GetPrintRegisterFormatForSize()
1447 const unsigned size = kQRegSizeInBytes; in PrintZRegistersForStructuredAccess()
1515 const unsigned size = kQRegSizeInBytes; in PrintPartialZRegister()
1634 (reg_size_in_bytes == kQRegSizeInBytes)); in PrintPartialAccess()
1813 address += kQRegSizeInBytes; in PrintZAccess()
1839 int lanes_per_q = kQRegSizeInBytes / esize_in_bytes; in PrintZStructAccess()
1897 address += kQRegSizeInBytes; in PrintPAccess()
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| D | assembler-aarch64.cc | 142 VIXL_ASSERT(literal->GetSize() == kQRegSizeInBytes); in place()
2331 VIXL_ASSERT(lane < (kQRegSizeInBytes / lane_size)); in LoadStoreStructSingle()
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| D | disasm-aarch64.cc | 6198 : kQRegSizeInBytes; in SubstituteRegisterField()
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