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Searched refs:ld1rb (Results 1 – 9 of 9) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12513 "lastb\003ld1\004ld1b\004ld1d\004ld1h\004ld1r\005ld1rb\005ld1rd\005ld1rh"
15144 …{ 1878 /* ld1rb */, AArch64::LD1RB_H_IMM, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1…
15145 …{ 1878 /* ld1rb */, AArch64::LD1RB_S_IMM, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1…
15146 …{ 1878 /* ld1rb */, AArch64::LD1RB_D_IMM, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1…
15147 …{ 1878 /* ld1rb */, AArch64::LD1RB_IMM, Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5…
15148 …{ 1878 /* ld1rb */, AArch64::LD1RB_IMM, Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1…
15149 …{ 1878 /* ld1rb */, AArch64::LD1RB_H_IMM, Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__R…
15150 …{ 1878 /* ld1rb */, AArch64::LD1RB_S_IMM, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__R…
15151 …{ 1878 /* ld1rb */, AArch64::LD1RB_D_IMM, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__R…
15152 …{ 1878 /* ld1rb */, AArch64::LD1RB_H_IMM, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1…
[all …]
DAArch64GenAsmWriter.inc22299 /* 3297 */ "ld1rb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
22300 /* 3322 */ "ld1rb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
22301 /* 3347 */ "ld1rb $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
22302 /* 3372 */ "ld1rb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
DAArch64GenAsmWriter1.inc23020 /* 3289 */ "ld1rb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23021 /* 3314 */ "ld1rb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23022 /* 3339 */ "ld1rb $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
23023 /* 3364 */ "ld1rb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td360 defm LD1RB_IMM : sve_mem_ld_dup<0b00, 0b00, "ld1rb", Z_b, ZPR8, uimm6s1>;
361 defm LD1RB_H_IMM : sve_mem_ld_dup<0b00, 0b01, "ld1rb", Z_h, ZPR16, uimm6s1>;
362 defm LD1RB_S_IMM : sve_mem_ld_dup<0b00, 0b10, "ld1rb", Z_s, ZPR32, uimm6s1>;
363 defm LD1RB_D_IMM : sve_mem_ld_dup<0b00, 0b11, "ld1rb", Z_d, ZPR64, uimm6s1>;
/external/vixl/test/aarch64/
Dtest-disasm-sve-aarch64.cc3459 COMPARE(ld1rb(z2.VnH(), p0.Zeroing(), SVEMemOperand(x30, 0)), in TEST()
3461 COMPARE(ld1rb(z14.VnS(), p2.Zeroing(), SVEMemOperand(x11, 63)), in TEST()
3463 COMPARE(ld1rb(z27.VnD(), p1.Zeroing(), SVEMemOperand(x29, 2)), in TEST()
3465 COMPARE(ld1rb(z0.VnB(), p3.Zeroing(), SVEMemOperand(sp, 59)), in TEST()
/external/vixl/src/aarch64/
Dassembler-aarch64.h4579 void ld1rb(const ZRegister& zt,
Dassembler-sve-aarch64.cc4156 void Assembler::ld1rb(const ZRegister& zt, in ld1rb() function in vixl::aarch64::Assembler
Dmacro-assembler-aarch64.h4831 &MacroAssembler::ld1rb, in Ld1rb()
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md8438 void ld1rb(const ZRegister& zt,