/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
D | AArch64GenAsmMatcher.inc | 12525 "b\007ldeorlh\006ldff1b\006ldff1d\006ldff1h\007ldff1sb\007ldff1sh\007ldf" 15862 …{ 2457 /* ldff1d */, AArch64::LDFF1D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg… 15863 …{ 2457 /* ldff1d */, AArch64::GLDFF1D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1… 15864 …{ 2457 /* ldff1d */, AArch64::LDFF1D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__… 15865 …{ 2457 /* ldff1d */, AArch64::GLDFF1D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg… 15866 …{ 2457 /* ldff1d */, AArch64::LDFF1D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg… 15867 …{ 2457 /* ldff1d */, AArch64::GLDFF1D_SCALED_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg… 15868 …{ 2457 /* ldff1d */, AArch64::GLDFF1D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Re… 15869 …{ 2457 /* ldff1d */, AArch64::GLDFF1D_SXTW_SCALED_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bA… 15870 …{ 2457 /* ldff1d */, AArch64::GLDFF1D_SXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_… [all …]
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D | AArch64GenAsmWriter.inc | 22230 /* 2081 */ "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" 22452 /* 6555 */ "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
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D | AArch64GenAsmWriter1.inc | 22951 /* 2081 */ "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" 23173 /* 6547 */ "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64SVEInstrInfo.td | 439 defm LDFF1D : sve_mem_cldff_ss<0b1111, "ldff1d", Z_d, ZPR64, GPR64shifted64>; 519 …defm GLDFF1D : sve_mem_64b_gld_vi_64_ptrs<0b1111, "ldff1d", uimm5s8, null_frag, … 536 …defm GLDFF1D : sve_mem_64b_gld_vs2_64_unscaled<0b1111, "ldff1d", null_frag, nxv2i64>; 549 …defm GLDFF1D : sve_mem_64b_gld_sv2_64_scaled<0b1111, "ldff1d", null_frag, ZP… 566 …defm GLDFF1D : sve_mem_64b_gld_vs_32_unscaled<0b1111, "ldff1d", null_frag, nul… 579 …defm GLDFF1D : sve_mem_64b_gld_sv_32_scaled<0b1111, "ldff1d", null_frag, null_frag, …
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/external/vixl/test/aarch64/ |
D | test-assembler-sve-aarch64.cc | 9056 Ld1Macro ldff1d = &MacroAssembler::Ldff1d; in TEST_SVE() local 9058 ldff1_scaled_offset_helper(kDRegSize, kDRegSize, ldff1d, ld1d); in TEST_SVE() 9163 Ld1Macro ldff1d = &MacroAssembler::Ldff1d; in sve_ldff1_scalar_plus_vector_32_unpacked_scaled_offset() local 9165 ldff1_32_unpacked_scaled_offset_helper(kDRegSize, ldff1d, ld1d, UXTW); in sve_ldff1_scalar_plus_vector_32_unpacked_scaled_offset() 9166 ldff1_32_unpacked_scaled_offset_helper(kDRegSize, ldff1d, ld1d, SXTW); in sve_ldff1_scalar_plus_vector_32_unpacked_scaled_offset() 9208 Ld1Macro ldff1d = &MacroAssembler::Ldff1d; in sve_ldff1_scalar_plus_vector_32_unpacked_unscaled_offset() local 9210 ldff1_32_unpacked_unscaled_offset_helper(kDRegSize, ldff1d, ld1d, UXTW); in sve_ldff1_scalar_plus_vector_32_unpacked_unscaled_offset() 9211 ldff1_32_unpacked_unscaled_offset_helper(kDRegSize, ldff1d, ld1d, SXTW); in sve_ldff1_scalar_plus_vector_32_unpacked_unscaled_offset() 9250 Ld1Macro ldff1d = &MacroAssembler::Ldff1d; in sve_ldff1_scalar_plus_vector_64_scaled_offset() local 9252 ldff1_64_scaled_offset_helper(kDRegSize, ldff1d, ld1d); in sve_ldff1_scalar_plus_vector_64_scaled_offset() [all …]
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D | test-disasm-sve-aarch64.cc | 3544 COMPARE(ldff1d(z19.VnD(), p1.Zeroing(), SVEMemOperand(z14.VnD())), in TEST() 3809 COMPARE(ldff1d(z23.VnD(), p5.Zeroing(), SVEMemOperand(x29, z31.VnD())), in TEST() 3825 COMPARE(ldff1d(z2.VnD(), p0.Zeroing(), SVEMemOperand(sp, z7.VnD(), LSL, 3)), in TEST() 3843 COMPARE(ldff1d(z24.VnD(), p3.Zeroing(), SVEMemOperand(x3, z24.VnD(), SXTW)), in TEST() 3859 COMPARE(ldff1d(z6.VnD(), p3.Zeroing(), SVEMemOperand(x3, z31.VnD(), SXTW, 3)), in TEST() 4369 COMPARE(ldff1d(z0.VnD(), p3.Zeroing(), SVEMemOperand(x15, x1, LSL, 3)), in TEST()
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/external/vixl/src/aarch64/ |
D | macro-assembler-sve-aarch64.cc | 1465 static_cast<SVELoad1Fn>(&Assembler::ldff1d)); in Ldff1d()
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D | assembler-aarch64.h | 4770 void ldff1d(const ZRegister& zt, 4802 void ldff1d(const ZRegister& zt, 4808 void ldff1d(const ZRegister& zt,
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D | assembler-sve-aarch64.cc | 4287 void Assembler::ldff1d(const ZRegister& zt, in ldff1d() function in vixl::aarch64::Assembler 4301 void Assembler::ldff1d(const ZRegister& zt, in ldff1d() function in vixl::aarch64::Assembler
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D | macro-assembler-aarch64.h | 5078 ldff1d(zt, pg, xn, zm); in Ldff1d() 5086 ldff1d(zt, pg, zn, imm5); in Ldff1d()
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/external/vixl/doc/aarch64/ |
D | supported-instructions-aarch64.md | 8770 void ldff1d(const ZRegister& zt, 8779 void ldff1d(const ZRegister& zt, 8789 void ldff1d(const ZRegister& zt,
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