Home
last modified time | relevance | path

Searched refs:lsr (Results 1 – 25 of 546) sorted by relevance

12345678910>>...22

/external/llvm/test/CodeGen/Hexagon/
Dremove_lsr.ll4 ; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)
5 ; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)
8 ; r17:16 = lsr(r11:10, #32)
11 ; r17:16 = lsr(r11:10, #32)
13 ; This makes the lsr instruction dead and it gets removed subsequently
32 %lsr.iv42 = phi i32 [ %lsr.iv.next, %for.body ], [ 2, %entry ]
33 %lsr.iv40 = phi i8* [ %scevgep41, %for.body ], [ %scevgep39, %entry ]
34 %lsr.iv37 = phi i8* [ %scevgep38, %for.body ], [ %scevgep36, %entry ]
35 %lsr.iv33 = phi %union.vect32* [ %scevgep34, %for.body ], [ %scevgep32, %entry ]
36 %lsr.iv29 = phi %union.vect32* [ %scevgep30, %for.body ], [ %scevgep28, %entry ]
[all …]
Dhwloop2.ll1 ; RUN: llc -disable-lsr -march=hexagon < %s | FileCheck %s
20 %lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ %n, %for.body.lr.ph ]
21 %lsr.iv1 = phi i32* [ %scevgep, %for.body ], [ %a, %for.body.lr.ph ]
22 %1 = load i32, i32* %lsr.iv1, align 4
26 %lsr.iv.next = add i32 %lsr.iv, -1
27 %scevgep = getelementptr i32, i32* %lsr.iv1, i32 1
28 %cmp = icmp eq i32 %lsr.iv.next, 0
/external/musl/src/string/arm/
Dmemcpy.S238 movmi r3, r3, lsr #8
240 movcs r3, r3, lsr #8
242 movcs r3, r3, lsr #8
249 mov r3, r3, lsr r12
259 mov r4, r5, lsr lr
265 mov r3, r5, lsr r12
293 orr r3, r3, r4, lsr #16
295 orr r4, r4, r5, lsr #16
297 orr r5, r5, r6, lsr #16
299 orr r6, r6, r7, lsr #16
[all …]
/external/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/
Dlsr-postinc-pos-addrspace.ll1 ; RUN: llc -march=amdgcn -mcpu=bonaire -print-lsr-output < %s 2>&1 | FileCheck %s
10 ; CHECK: %lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb ], [ 2, %entry ]
11 ; CHECK: %lsr.iv = phi i32 [ %lsr.iv.next, %bb ], [ %{{[0-9]+}}, %entry ]
12 ; CHECK: %lsr.iv.next = add i32 %lsr.iv, -1
13 ; CHECK: %lsr.iv.next2 = add i32 %lsr.iv1, -2
17 ; CHECK: inttoptr i32 %lsr.iv.next2 to i8 addrspace(3)*
41 ; CHECK: %lsr.iv1 = phi i64
42 ; CHECK: %lsr.iv = phi i64
43 ; CHECK: %lsr.iv.next = add i64 %lsr.iv, -1
44 ; CHECK: %lsr.iv.next2 = add i64 %lsr.iv1, -2
[all …]
/external/icu/tools/cldr/cldr-to-icu/src/test/java/org/unicode/icu/tool/cldrtoicu/localedistance/
DLikelySubtagsBuilderTest.java14 import static org.unicode.icu.tool.cldrtoicu.localedistance.TestData.lsr;
75 lsr(""), in testLikelySubtags()
76 lsr("skip-script"), in testLikelySubtags()
78 lsr("en-Latn-US"), in testLikelySubtags()
79 lsr("pt-Latn-BR"), in testLikelySubtags()
80 lsr("zh-Hans-CN"), in testLikelySubtags()
81 lsr("zh-Hant-TW")) in testLikelySubtags()
89 "*-*-*", lsr("en-Latn-US"), in testLikelySubtags()
90 "*-*-BR", lsr("pt-Latn-BR"), in testLikelySubtags()
91 "*-Latn-*", lsr("en-Latn-US"), in testLikelySubtags()
[all …]
/external/llvm/test/Analysis/BasicAA/
Dphi-spec-order.ll17 …%lsr.iv4 = phi [16000 x double]* [ %i11, %for.body4 ], [ bitcast (double* getelementptr inbounds (…
19 %lsr.iv1 = phi [16000 x double]* [ %i10, %for.body4 ], [ @X, %for.cond2.preheader ]
21 ; CHECK: NoAlias:{{[ \t]+}}[16000 x double]* %lsr.iv1, [16000 x double]* %lsr.iv4
23 %lsr.iv = phi i32 [ %lsr.iv.next, %for.body4 ], [ 16000, %for.cond2.preheader ]
24 %lsr.iv46 = bitcast [16000 x double]* %lsr.iv4 to <4 x double>*
25 %lsr.iv12 = bitcast [16000 x double]* %lsr.iv1 to <4 x double>*
26 %scevgep11 = getelementptr <4 x double>, <4 x double>* %lsr.iv46, i64 -2
29 store <4 x double> %add, <4 x double>* %lsr.iv12, align 32
30 %scevgep10 = getelementptr <4 x double>, <4 x double>* %lsr.iv46, i64 -1
33 %scevgep9 = getelementptr <4 x double>, <4 x double>* %lsr.iv12, i64 1
[all …]
/external/llvm/test/CodeGen/X86/
Dfast-isel-trunc-kill-subreg.ll21 %lsr.iv3 = phi i64 [ %lsr.iv.next4, %bb241 ], [ %tmp12, %bb ]
22 %lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb241 ], [ 0, %bb ]
23 %lsr.iv.next2 = add nuw nsw i32 %lsr.iv1, 1
24 %lsr.iv.next4 = add i64 %lsr.iv3, 32
25 %exitcond = icmp eq i32 %lsr.iv.next2, 8
33 %lsr.iv = phi i32 [ %lsr.iv.next, %bb270 ], [ %tmp18, %.preheader.preheader ]
34 %lsr.iv.next = add i32 %lsr.iv, 4
35 %tmp272 = icmp slt i32 %lsr.iv.next, 100
Dragreedy-bug.ll49 %lsr.iv27 = phi i64 [ %lsr.iv.next28, %if.end17 ], [ 0, %if.end ]
50 %scevgep55 = getelementptr i8, i8* %4, i64 %lsr.iv27
71 %sunkaddr58 = add i64 %sunkaddr, %lsr.iv27
93 %sunkaddr61 = add i64 %sunkaddr60, %lsr.iv27
97 %sunkaddr64 = add i64 %sunkaddr63, %lsr.iv27
103 %lsr.iv.next28 = add i64 %lsr.iv27, 1
117 %sunkaddr70 = add i64 %sunkaddr69, %lsr.iv27
128 %sunkaddr73 = add i64 %sunkaddr72, %lsr.iv27
138 %scevgep53 = getelementptr i8, i8* %scevgep52, i64 %lsr.iv27
146 %scevgep48 = getelementptr i8, i8* %scevgep47, i64 %lsr.iv27
[all …]
/external/llvm/test/MC/ARM/
Darm_addrmode2.s5 @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
9 @ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
13 @ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
17 @ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6]
21 ldrt r1, [r0], r2, lsr #3
25 ldrbt r1, [r0], r2, lsr #3
29 strt r1, [r0], r2, lsr #3
33 strbt r1, [r0], r2, lsr #3
38 @ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7]
39 @ CHECK: ldrb r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xf0,0xe7]
[all …]
Darm-shift-encoding.s4 ldr r0, [r0, r0, lsr #32]
5 ldr r0, [r0, r0, lsr #16]
14 @ CHECK: ldr r0, [r0, r0, lsr #32] @ encoding: [0x20,0x00,0x90,0xe7]
15 @ CHECK: ldr r0, [r0, r0, lsr #16] @ encoding: [0x20,0x08,0x90,0xe7]
24 pld [r0, r0, lsr #32]
25 pld [r0, r0, lsr #16]
34 @ CHECK: [r0, r0, lsr #32] @ encoding: [0x20,0xf0,0xd0,0xf7]
35 @ CHECK: [r0, r0, lsr #16] @ encoding: [0x20,0xf8,0xd0,0xf7]
44 str r0, [r0, r0, lsr #32]
45 str r0, [r0, r0, lsr #16]
[all …]
Dthumb-shift-encoding.s8 sbc.w r1, r8, r9, lsr #32
9 sbc.w r2, r7, r10, lsr #16
18 @ CHECK: sbc.w r1, r8, r9, lsr #32 @ encoding: [0x68,0xeb,0x19,0x01]
19 @ CHECK: sbc.w r2, r7, r10, lsr #16 @ encoding: [0x67,0xeb,0x1a,0x42]
28 and.w r1, r8, r9, lsr #32
29 and.w r2, r7, r10, lsr #16
38 @ CHECK: and.w r1, r8, r9, lsr #32 @ encoding: [0x08,0xea,0x19,0x01]
39 @ CHECK: and.w r2, r7, r10, lsr #16 @ encoding: [0x07,0xea,0x1a,0x42]
Dbasic-arm-instructions.s72 adc r4, r5, r6, lsr #1
73 adc r4, r5, r6, lsr #31
74 adc r4, r5, r6, lsr #32
83 adc r6, r7, r8, lsr r9
92 adc r4, r5, lsr #1
93 adc r4, r5, lsr #31
94 adc r4, r5, lsr #32
102 adc r6, r7, lsr r9
111 @ CHECK: adc r4, r5, r6, lsr #1 @ encoding: [0xa6,0x40,0xa5,0xe0]
112 @ CHECK: adc r4, r5, r6, lsr #31 @ encoding: [0xa6,0x4f,0xa5,0xe0]
[all …]
/external/llvm/test/MC/AArch64/
Darm64-logical-encoding.s54 and w1, w2, w3, lsr #2
55 and x1, x2, x3, lsr #2
65 ; CHECK: and w1, w2, w3, lsr #2 ; encoding: [0x41,0x08,0x43,0x0a]
66 ; CHECK: and x1, x2, x3, lsr #2 ; encoding: [0x41,0x08,0x43,0x8a]
76 ands w1, w2, w3, lsr #2
77 ands x1, x2, x3, lsr #2
87 ; CHECK: ands w1, w2, w3, lsr #2 ; encoding: [0x41,0x08,0x43,0x6a]
88 ; CHECK: ands x1, x2, x3, lsr #2 ; encoding: [0x41,0x08,0x43,0xea]
98 bic w1, w2, w3, lsr #3
99 bic x1, x2, x3, lsr #3
[all …]
/external/capstone/suite/MC/ARM/
Darm-shift-encoding.s.cs3 0x20,0x00,0x90,0xe7 = ldr r0, [r0, r0, lsr #32]
4 0x20,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsr #16]
12 0x20,0xf0,0xd0,0xf7 = pld [r0, r0, lsr #32]
13 0x20,0xf8,0xd0,0xf7 = pld [r0, r0, lsr #16]
21 0x20,0x00,0x80,0xe7 = str r0, [r0, r0, lsr #32]
22 0x20,0x08,0x80,0xe7 = str r0, [r0, r0, lsr #16]
34 0x29,0x10,0xa8,0xe0 = adc r1, r8, r9, lsr #32
35 0x2f,0x28,0xa7,0xe0 = adc r2, r7, pc, lsr #16
43 0x28,0x00,0x51,0xe1 = cmp r1, r8, lsr #32
44 0x27,0x08,0x52,0xe1 = cmp r2, r7, lsr #16
Dbasic-arm-instructions.s.cs17 0xa6,0x40,0xa5,0xe0 = adc r4, r5, r6, lsr #1
18 0xa6,0x4f,0xa5,0xe0 = adc r4, r5, r6, lsr #31
19 0x26,0x40,0xa5,0xe0 = adc r4, r5, r6, lsr #32
26 0x38,0x69,0xa7,0xe0 = adc r6, r7, r8, lsr r9
33 0xa5,0x40,0xa4,0xe0 = adc r4, r4, r5, lsr #1
34 0xa5,0x4f,0xa4,0xe0 = adc r4, r4, r5, lsr #31
35 0x25,0x40,0xa4,0xe0 = adc r4, r4, r5, lsr #32
43 0x37,0x69,0xa6,0xe0 = adc r6, r6, r7, lsr r9
50 0xa6,0x42,0x85,0xe0 = add r4, r5, r6, lsr #5
51 0xa6,0x42,0x85,0xe0 = add r4, r5, r6, lsr #5
[all …]
Darm_addrmode2.s.cs3 0xa2,0x11,0xb0,0xe6 = ldrt r1, [r0], r2, lsr #3
6 0xa2,0x11,0xf0,0xe6 = ldrbt r1, [r0], r2, lsr #3
9 0xa2,0x11,0xa0,0xe6 = strt r1, [r0], r2, lsr #3
12 0xa2,0x11,0xe0,0xe6 = strbt r1, [r0], r2, lsr #3
14 0xa2,0x11,0xb0,0xe7 = ldr r1, [r0, r2, lsr #3]!
15 0xa2,0x11,0xf0,0xe7 = ldrb r1, [r0, r2, lsr #3]!
/external/llvm/test/MC/Disassembler/Hexagon/
Dxtype_shift.txt8 # CHECK: r17:16 = lsr(r21:20, #31)
14 # CHECK: r17 = lsr(r21, #31)
22 # CHECK: r17:16 -= lsr(r21:20, #31)
28 # CHECK: r17:16 += lsr(r21:20, #31)
34 # CHECK: r17 -= lsr(r21, #31)
40 # CHECK: r17 += lsr(r21, #31)
48 # CHECK: r17 = add(#21, lsr(r17, #23))
50 # CHECK: r17 = sub(#21, lsr(r17, #23))
60 # CHECK: r17:16 &= lsr(r21:20, #31)
66 # CHECK: r17:16 |= lsr(r21:20, #31)
[all …]
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_shift.ll15 declare i64 @llvm.hexagon.S2.lsr.i.p(i64, i32)
17 %z = call i64 @llvm.hexagon.S2.lsr.i.p(i64 %a, i32 0)
20 ; CHECK: = lsr({{.*}}, #0)
36 declare i32 @llvm.hexagon.S2.lsr.i.r(i32, i32)
38 %z = call i32 @llvm.hexagon.S2.lsr.i.r(i32 %a, i32 0)
41 ; CHECK: = lsr({{.*}}, #0)
58 declare i64 @llvm.hexagon.S2.lsr.i.p.nac(i64, i64, i32)
60 %z = call i64 @llvm.hexagon.S2.lsr.i.p.nac(i64 %a, i64 %b, i32 0)
63 ; CHECK: -= lsr({{.*}}, #0)
79 declare i64 @llvm.hexagon.S2.lsr.i.p.acc(i64, i64, i32)
[all …]
/external/llvm/test/CodeGen/AArch64/
Dragreedy-csr.ll54 %lsr.iv27 = phi i64 [ %lsr.iv.next28, %if.end17 ], [ 0, %if.end ]
55 %scevgep55 = getelementptr i8, i8* %4, i64 %lsr.iv27
76 %sunkaddr58 = add i64 %sunkaddr, %lsr.iv27
98 %sunkaddr61 = add i64 %sunkaddr60, %lsr.iv27
102 %sunkaddr64 = add i64 %sunkaddr63, %lsr.iv27
108 %lsr.iv.next28 = add i64 %lsr.iv27, 1
122 %sunkaddr70 = add i64 %sunkaddr69, %lsr.iv27
133 %sunkaddr73 = add i64 %sunkaddr72, %lsr.iv27
143 %scevgep53 = getelementptr i8, i8* %scevgep52, i64 %lsr.iv27
151 %scevgep48 = getelementptr i8, i8* %scevgep47, i64 %lsr.iv27
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-logical.txt64 # CHECK: and w1, w2, w3, lsr #2
65 # CHECK: and x1, x2, x3, lsr #2
86 # CHECK: ands w1, w2, w3, lsr #2
87 # CHECK: ands x1, x2, x3, lsr #2
108 # CHECK: bic w1, w2, w3, lsr #3
109 # CHECK: bic x1, x2, x3, lsr #3
130 # CHECK: bics w1, w2, w3, lsr #3
131 # CHECK: bics x1, x2, x3, lsr #3
152 # CHECK: eon w1, w2, w3, lsr #4
153 # CHECK: eon x1, x2, x3, lsr #4
[all …]
/external/llvm/test/Analysis/ScalarEvolution/
Dincorrect-offset-scaling.ll15 ; CHECK: %lsr.iv = phi i64 [ 0, %L{{[^ ]+}} ], [ %lsr.iv.next, %L2 ]
16 ; CHECK-NOT: %lsr.iv = phi i64 [ -1, %L{{[^ ]+}} ], [ %lsr.iv.next, %L2 ]
39 ; CHECK %2 = mul i64 %lsr.iv, %r3
45 ; CHECK %5 = mul i64 %lsr.iv, %r3
/external/icu/tools/cldr/cldr-to-icu/src/main/java/org/unicode/icu/tool/cldrtoicu/localedistance/
DLikelySubtagsBuilder.java169 lsrToIndex.apply(lsr("", "", "")); in build()
173 lsrToIndex.apply(lsr("skip", "script", "")); in build()
238 (region, lsr) -> languageOrScriptSpan.with( in writeRegions()
240 span -> span.putPrefixAndValue(lsrToIndex.apply(lsr)))); in writeRegions()
274 set(lsrTable, "und", "Latn", "", lsr("en", "Latn", "US")); in makeTable()
290 …lsrTable.get("*").get("*").forEach((key, lsr) -> set(lsrTable, "und", lsr.script, lsr.region, lsr)… in makeTable()
317 String language, String script, String region, LSR lsr) { in set() argument
320 regionTable.put(subtagOrStar(region), lsr); in set() local
336 return lsr(m.group(1), m.group(2), m.group(3)); in lsrFromLocaleID()
340 private static LSR lsr(String language, String script, String region) { in lsr() method in LikelySubtagsBuilder
/external/llvm/test/CodeGen/PowerPC/
Dstdux-constuse.ll1 ; RUN: llc -mcpu=a2 -disable-lsr < %s | FileCheck %s
15 %lsr.iv = phi i32 [ %lsr.iv.next, %for.body4 ], [ 16000, %for.cond2.preheader ]
25 %lsr.iv.next = add i32 %lsr.iv, -16
26 %exitcond.15 = icmp eq i32 %lsr.iv.next, 0
/external/cronet/third_party/boringssl/linux-aarch64/crypto/fipsmodule/
Dp256_beeu-armv8-asm-linux.S101 lsr x25, x25, x13
104 lsr x26, x26, x13
109 lsr x27, x27, x13
114 lsr x28, x28, x13
139 lsr x7, x7, #1
165 lsr x21, x21, x13
168 lsr x22, x22, x13
173 lsr x23, x23, x13
178 lsr x24, x24, x13
203 lsr x12, x12, #1
/external/boringssl/apple-aarch64/crypto/fipsmodule/
Dp256_beeu-armv8-asm-apple.S101 lsr x25, x25, x13
104 lsr x26, x26, x13
109 lsr x27, x27, x13
114 lsr x28, x28, x13
139 lsr x7, x7, #1
165 lsr x21, x21, x13
168 lsr x22, x22, x13
173 lsr x23, x23, x13
178 lsr x24, x24, x13
203 lsr x12, x12, #1

12345678910>>...22