Searched refs:mtilea (Results 1 – 16 of 16) sorted by relevance
| /external/libdrm/radeon/ |
| D | radeon_surface.c | 675 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea; in eg_surface_init_2d()
676 mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea; in eg_surface_init_2d()
746 switch (surf->mtilea) { in eg_surface_sanity()
756 if (surf_man->hw_info.num_banks < surf->mtilea) { in eg_surface_sanity()
921 surf->mtilea = surf_man->hw_info.num_banks; in eg_surface_best()
928 if (surf->mtilea > 8) { in eg_surface_best()
929 surf->mtilea = 8; in eg_surface_best()
1020 surf->mtilea = 1 << (log2_int(h_over_w) >> 1); in eg_surface_best()
1320 surf->mtilea = 1; in si_surface_sanity()
1399 …si_gb_tile_mode(gb_tile_mode, NULL, NULL, &surf->mtilea, &surf->bankw, &surf->bankh, &surf->tile_s… in si_surface_sanity()
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| D | radeon_surface.h | 132 uint32_t mtilea; member
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| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_surface.c | 153 surf_drm->mtilea = surf_ws->u.legacy.mtilea; in surf_winsys_to_drm()
195 surf_ws->u.legacy.mtilea = surf_drm->mtilea; in surf_drm_to_winsys()
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| D | radeon_drm_bo.c | 905 …surf->u.legacy.mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_T… in radeon_bo_get_metadata()
927 …md->u.legacy.mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TIL… in radeon_bo_get_metadata()
960 args.tiling_flags |= (surf->u.legacy.mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) << in radeon_bo_set_metadata()
985 args.tiling_flags |= (md->u.legacy.mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) << in radeon_bo_set_metadata()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | radeon_video.c | 179 surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea; in rvid_join_surfaces()
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| D | r600_texture.c | 287 metadata->u.legacy.mtilea = surface->u.legacy.mtilea; in r600_texture_init_metadata()
303 surf->u.legacy.mtilea = metadata->u.legacy.mtilea; in r600_surface_import_metadata()
614 fmask.u.legacy.mtilea = rtex->surface.u.legacy.mtilea; in r600_texture_get_fmask_info()
844 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea, in r600_print_texture_info()
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| D | radeon_uvd.c | 1243 assert(luma->u.legacy.mtilea == chroma->u.legacy.mtilea); in ruvd_set_dt_surfaces()
1248 …code.dt_surf_tile_config |= RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->u.legacy.mtilea)); in ruvd_set_dt_surfaces()
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| D | evergreen_state.c | 809 macro_aspect = tmp->surface.u.legacy.mtilea; in evergreen_fill_tex_resource_words()
1158 macro_aspect = rtex->surface.u.legacy.mtilea; in evergreen_set_color_surface_common()
1377 macro_aspect = rtex->surface.u.legacy.mtilea; in evergreen_init_depth_surface()
3822 mt_aspect = eg_macro_tile_aspect(rsrc->surface.u.legacy.mtilea); in evergreen_dma_copy_tile()
3847 mt_aspect = eg_macro_tile_aspect(rdst->surface.u.legacy.mtilea); in evergreen_dma_copy_tile()
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| /external/mesa3d/src/amd/common/ |
| D | ac_surface.h | 106 unsigned mtilea : 4; /* max 8 */ member
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| D | ac_surface.c | 734 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio; in gfx6_surface_settings()
983 surf->u.legacy.bankh && surf->u.legacy.mtilea && surf->u.legacy.tile_split) { in gfx6_compute_surface()
989 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea; in gfx6_compute_surface()
2241 surf->u.legacy.mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in ac_surface_set_bo_metadata()
2296 *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(surf->u.legacy.mtilea)); in ac_surface_get_bo_metadata()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_radeon_winsys.h | 140 unsigned mtilea; member
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| D | radv_image.c | 337 surface->u.legacy.mtilea = md->u.legacy.mtilea; in radv_patch_surface_from_metadata()
1241 metadata->u.legacy.mtilea = surface->u.legacy.mtilea; in radv_init_metadata()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | radeon_winsys.h | 224 unsigned mtilea; member
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| D | radeon_uvd.c | 1477 assert(luma->u.legacy.mtilea == chroma->u.legacy.mtilea); in si_uvd_set_dt_surfaces()
1483 RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->u.legacy.mtilea)); in si_uvd_set_dt_surfaces()
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| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| D | radv_amdgpu_bo.c | 805 tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->u.legacy.mtilea)); in radv_amdgpu_winsys_bo_set_metadata()
850 md->u.legacy.mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in radv_amdgpu_winsys_bo_get_metadata()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_texture.c | 895 tex->surface.u.legacy.mtilea, tex->surface.u.legacy.tile_split, in si_print_texture_info()
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