| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_surface.c | 72 level_drm->nblk_x = level_ws->nblk_x; in surf_level_winsys_to_drm()
74 level_drm->pitch_bytes = level_ws->nblk_x * bpe; in surf_level_winsys_to_drm()
84 level_ws->nblk_x = level_drm->nblk_x; in surf_level_drm_to_winsys()
87 assert(level_drm->nblk_x * bpe == level_drm->pitch_bytes); in surf_level_drm_to_winsys()
260 unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width*8); in si_compute_cmask()
336 width = align(surf->u.legacy.level[0].nblk_x, cl_width * 8); in si_compute_htile()
411 (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64; in radeon_winsys_surface_init()
417 surf_ws->u.legacy.fmask.pitch_in_pixels = fmask.u.legacy.level[0].nblk_x; in radeon_winsys_surface_init()
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| D | radeon_drm_bo.c | 966 args.pitch = surf->u.legacy.level[0].nblk_x * surf->bpe; in radeon_bo_set_metadata()
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| /external/libdrm/radeon/ |
| D | radeon_surface.c | 176 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; in surf_minify()
181 if (surflevel->nblk_x < xalign || surflevel->nblk_y < yalign) { in surf_minify()
186 surflevel->nblk_x = ALIGN(surflevel->nblk_x, xalign); in surf_minify()
191 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; in surf_minify()
585 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; in eg_surf_minify()
590 if (surflevel->nblk_x < mtilew || surflevel->nblk_y < mtileh) { in eg_surf_minify()
595 surflevel->nblk_x = ALIGN(surflevel->nblk_x, mtilew); in eg_surf_minify()
600 mtile_pr = surflevel->nblk_x / mtilew; in eg_surf_minify()
605 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; in eg_surf_minify()
1436 surflevel->nblk_x = (next_power_of_two(surflevel->npix_x) + surf->blk_w - 1) / surf->blk_w; in si_surf_minify()
[all …]
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| D | radeon_surface.h | 75 uint32_t nblk_x; member
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | radeon_vce_40_2_2.c | 85 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch in create()
86 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch in create()
315 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch in encode()
316 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch in encode()
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| D | radeon_vce_50.c | 125 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch in encode()
126 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch in encode()
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| D | radeon_vce_52.c | 196 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch in create()
197 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch in create()
272 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch in encode()
273 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch in encode()
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| D | radeon_vce.c | 223 pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128); in si_vce_frame_offset()
451 ? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) * in si_vce_create_encoder()
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| D | radeon_uvd_enc_1_1.c | 760 enc->enc_pic.ctx_buf.rec_luma_pitch = (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); in radeon_uvd_enc_ctx()
762 (enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); in radeon_uvd_enc_ctx()
879 (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); in radeon_uvd_enc_encode_params_hevc()
881 (enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); in radeon_uvd_enc_encode_params_hevc()
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| D | radeon_uvd_enc.c | 326 ? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) * in radeon_uvd_create_encoder()
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| D | radeon_vcn_enc.c | 441 ? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) * in radeon_create_encoder()
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| D | radeon_uvd.c | 1443 msg->body.decode.dt_pitch = luma->u.legacy.level[0].nblk_x * luma->blk_w; in si_uvd_set_dt_surfaces()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_texture.c | 180 *stride = rtex->surface.u.legacy.level[level].nblk_x * in r600_texture_get_offset()
193 rtex->surface.u.legacy.level[level].nblk_x + in r600_texture_get_offset()
254 pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) { in r600_init_surface()
258 surface->u.legacy.level[0].nblk_x = pitch_in_bytes_override / bpe; in r600_init_surface()
289 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe; in r600_texture_init_metadata()
459 stride = rtex->surface.u.legacy.level[0].nblk_x * in r600_texture_get_info()
648 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64; in r600_texture_get_fmask_info()
653 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x; in r600_texture_get_fmask_info()
798 width = align(rtex->surface.u.legacy.level[0].nblk_x, cl_width * 8); in r600_texture_get_htile_size()
876 rtex->surface.u.legacy.level[i].nblk_x, in r600_print_texture_info()
[all …]
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| D | radeon_vce.c | 234 pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128); in rvce_frame_offset()
455 cpb_size = align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) * in rvce_create_encoder()
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| D | r600_state.c | 726 …pitch = tmp->surface.u.legacy.level[offset_level].nblk_x * util_format_get_blockwidth(state->forma… in r600_create_sampler_view_custom()
831 pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1; in r600_init_color_surface()
832 …slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) … in r600_init_color_surface()
1045 pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1; in r600_init_depth_surface()
1046 …slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) … in r600_init_depth_surface()
2875 …slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[sr… in r600_dma_copy_tile()
2894 …slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[ds… in r600_dma_copy_tile()
2984 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe; in r600_dma_copy()
2985 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe; in r600_dma_copy()
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| D | evergreen_state.c | 794 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(params->pipe_format); in evergreen_fill_tex_resource_words()
1135 pitch = (rtex->surface.u.legacy.level[level].nblk_x) / 8 - 1; in evergreen_set_color_surface_common()
1136 …slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) … in evergreen_set_color_surface_common()
1398 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); in evergreen_init_depth_surface()
1403 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) | in evergreen_init_depth_surface()
1405 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x * in evergreen_init_depth_surface()
3804 …slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[sr… in evergreen_dma_copy_tile()
3829 …slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[ds… in evergreen_dma_copy_tile()
3926 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe; in evergreen_dma_copy()
3927 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe; in evergreen_dma_copy()
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| D | radeon_uvd.c | 1209 msg->body.decode.dt_pitch = luma->u.legacy.level[0].nblk_x * luma->blk_w; in ruvd_set_dt_surfaces()
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| /external/mesa3d/src/amd/common/ |
| D | ac_surface.h | 90 unsigned nblk_x : 15; member
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| D | ac_surface.c | 524 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x; in gfx6_compute_level()
526 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x; in gfx6_compute_level()
541 surf_level->nblk_x = AddrSurfInfoOut->pitch; in gfx6_compute_level()
808 unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width * 8); in ac_compute_cmask()
1095 if (surf->u.legacy.stencil_level[level].nblk_x != surf->u.legacy.level[level].nblk_x) in gfx6_compute_surface()
1098 surf->u.legacy.level[level].nblk_x = surf->u.legacy.stencil_level[level].nblk_x; in gfx6_compute_surface()
2473 surf->u.legacy.level[0].nblk_x = pitch; in ac_surface_override_offset_stride()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | cik_sdma.c | 222 unsigned dst_pitch = sdst->surface.u.legacy.level[dst_level].nblk_x; in cik_sdma_copy_texture()
223 unsigned src_pitch = ssrc->surface.u.legacy.level[src_level].nblk_x; in cik_sdma_copy_texture()
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| D | si_texture.c | 200 *stride = tex->surface.u.legacy.level[level].nblk_x * tex->surface.bpe; in si_texture_get_offset()
211 (box->y / tex->surface.blk_h * tex->surface.u.legacy.level[level].nblk_x + in si_texture_get_offset()
614 *value = tex->surface.u.legacy.level[0].nblk_x * tex->surface.bpe; in si_resource_get_param()
940 u_minify(tex->buffer.b.b.depth0, i), tex->surface.u.legacy.level[i].nblk_x, in si_print_texture_info()
957 tex->surface.u.legacy.stencil_level[i].nblk_x, in si_print_texture_info()
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| D | si_state.c | 2453 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); in si_init_depth_surface()
2489 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) | in si_init_depth_surface()
2492 S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x * levelinfo->nblk_y) / 64 - 1); in si_init_depth_surface()
3059 pitch_tile_max = level_info->nblk_x / 8 - 1; in si_emit_framebuffer_state()
3060 slice_tile_max = level_info->nblk_x * level_info->nblk_y / 64 - 1; in si_emit_framebuffer_state()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_image.c | 734 unsigned pitch = base_level_info->nblk_x * block_width; in si_set_mutable_tex_desc_fields()
1243 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe; in radv_init_metadata()
1893 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe; in radv_GetImageSubresourceLayout()
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| D | radv_device.c | 6771 pitch_tile_max = level_info->nblk_x / 8 - 1; in radv_initialise_color_surface()
6772 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1; in radv_initialise_color_surface()
7133 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) | in radv_initialise_ds_surface()
7135 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1); in radv_initialise_ds_surface()
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| D | radv_meta_bufimage.c | 1653 stride = surf->image->planes[0].surface.u.legacy.level[0].nblk_x * 3; in get_image_stride_for_r32g32b32()
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