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Searched refs:nblk_y (Results 1 – 18 of 18) sorted by relevance

/external/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_surface.c73 level_drm->nblk_y = level_ws->nblk_y; in surf_level_winsys_to_drm()
85 level_ws->nblk_y = level_drm->nblk_y; in surf_level_drm_to_winsys()
261 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8); in si_compute_cmask()
337 height = align(surf->u.legacy.level[0].nblk_y, cl_height * 8); in si_compute_htile()
411 (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64; in radeon_winsys_surface_init()
/external/libdrm/radeon/
Dradeon_surface.c177 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; in surf_minify()
181 if (surflevel->nblk_x < xalign || surflevel->nblk_y < yalign) { in surf_minify()
187 surflevel->nblk_y = ALIGN(surflevel->nblk_y, yalign); in surf_minify()
192 surflevel->slice_size = (uint64_t)surflevel->pitch_bytes * surflevel->nblk_y; in surf_minify()
586 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; in eg_surf_minify()
590 if (surflevel->nblk_x < mtilew || surflevel->nblk_y < mtileh) { in eg_surf_minify()
596 surflevel->nblk_y = ALIGN(surflevel->nblk_y, mtileh); in eg_surf_minify()
602 mtile_ps = (mtile_pr * surflevel->nblk_y) / mtileh; in eg_surf_minify()
1437 surflevel->nblk_y = (next_power_of_two(surflevel->npix_y) + surf->blk_h - 1) / surf->blk_h; in si_surf_minify()
1441 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; in si_surf_minify()
[all …]
Dradeon_surface.h76 uint32_t nblk_y; member
/external/mesa3d/src/gallium/drivers/radeon/
Dradeon_vce_40_2_2.c87 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16) / 8); // encRefYHeightInQw in create()
314 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch in encode()
Dradeon_vce.c224 vpitch = align(enc->luma->u.legacy.level[0].nblk_y, 16); in si_vce_frame_offset()
452 align(tmp_surf->u.legacy.level[0].nblk_y, 32) in si_vce_create_encoder()
Dradeon_vce_50.c124 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch in encode()
Dradeon_uvd_enc.c327 align(tmp_surf->u.legacy.level[0].nblk_y, 32) in radeon_uvd_create_encoder()
Dradeon_vce_52.c198 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16) / 8); // encRefYHeightInQw in create()
271 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch in encode()
Dradeon_vcn_enc.c442 align(tmp_surf->u.legacy.level[0].nblk_y, 32) in radeon_create_encoder()
/external/mesa3d/src/amd/common/
Dac_surface.h91 unsigned nblk_y : 15; member
Dac_surface.c542 surf_level->nblk_y = AddrSurfInfoOut->height; in gfx6_compute_level()
809 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height * 8); in ac_compute_cmask()
2475 ((uint64_t)pitch * surf->u.legacy.level[0].nblk_y * surf->bpe) / 4; in ac_surface_override_offset_stride()
/external/mesa3d/src/gallium/drivers/r600/
Dradeon_vce.c235 vpitch = align(enc->luma->u.legacy.level[0].nblk_y, 16); in rvce_frame_offset()
456 align(tmp_surf->u.legacy.level[0].nblk_y, 32); in rvce_create_encoder()
Dr600_texture.c260 ((uint64_t)pitch_in_bytes_override * surface->u.legacy.level[0].nblk_y) / 4; in r600_init_surface()
648 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64; in r600_texture_get_fmask_info()
799 height = align(rtex->surface.u.legacy.level[0].nblk_y, cl_height * 8); in r600_texture_get_htile_size()
877 rtex->surface.u.legacy.level[i].nblk_y, in r600_print_texture_info()
895 rtex->surface.u.legacy.stencil_level[i].nblk_y, in r600_print_texture_info()
Dr600_state.c832 …slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) … in r600_init_color_surface()
1046 …slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) … in r600_init_depth_surface()
1069 surf->db_prefetch_limit = (rtex->surface.u.legacy.level[level].nblk_y / 8) - 1; in r600_init_depth_surface()
2875 …surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8); in r600_dma_copy_tile()
2894 …surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8); in r600_dma_copy_tile()
Devergreen_state.c1136 …slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) … in evergreen_set_color_surface_common()
1398 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); in evergreen_init_depth_surface()
1404 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1); in evergreen_init_depth_surface()
1406 levelinfo->nblk_y / 64 - 1); in evergreen_init_depth_surface()
3804 …surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8); in evergreen_dma_copy_tile()
3829 …surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8); in evergreen_dma_copy_tile()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state.c2453 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); in si_init_depth_surface()
2490 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1); in si_init_depth_surface()
2492 S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x * levelinfo->nblk_y) / 64 - 1); in si_init_depth_surface()
3060 slice_tile_max = level_info->nblk_x * level_info->nblk_y / 64 - 1; in si_emit_framebuffer_state()
Dsi_texture.c941 tex->surface.u.legacy.level[i].nblk_y, tex->surface.u.legacy.level[i].mode, in si_print_texture_info()
958 tex->surface.u.legacy.stencil_level[i].nblk_y, in si_print_texture_info()
/external/mesa3d/src/amd/vulkan/
Dradv_device.c6772 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1; in radv_initialise_color_surface()
7134 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1); in radv_initialise_ds_surface()
7135 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1); in radv_initialise_ds_surface()