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Searched refs:num_opcodes (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/amd/compiler/
Daco_ir.h1793 const int16_t opcode_gfx7[static_cast<int>(aco_opcode::num_opcodes)];
1794 const int16_t opcode_gfx9[static_cast<int>(aco_opcode::num_opcodes)];
1795 const int16_t opcode_gfx10[static_cast<int>(aco_opcode::num_opcodes)];
1796 const std::bitset<static_cast<int>(aco_opcode::num_opcodes)> can_use_input_modifiers;
1797 const std::bitset<static_cast<int>(aco_opcode::num_opcodes)> can_use_output_modifiers;
1798 const std::bitset<static_cast<int>(aco_opcode::num_opcodes)> is_atomic;
1799 const char *name[static_cast<int>(aco_opcode::num_opcodes)];
1800 const aco::Format format[static_cast<int>(aco_opcode::num_opcodes)];
1802 const unsigned operand_size[static_cast<int>(aco_opcode::num_opcodes)];
1803 const unsigned definition_size[static_cast<int>(aco_opcode::num_opcodes)];
Daco_lower_to_hw_instr.cpp164 case iadd64: return aco_opcode::num_opcodes; in get_reduce_opcode()
165 case imul64: return aco_opcode::num_opcodes; in get_reduce_opcode()
168 case imin64: return aco_opcode::num_opcodes; in get_reduce_opcode()
169 case imax64: return aco_opcode::num_opcodes; in get_reduce_opcode()
170 case umin64: return aco_opcode::num_opcodes; in get_reduce_opcode()
171 case umax64: return aco_opcode::num_opcodes; in get_reduce_opcode()
174 case iand64: return aco_opcode::num_opcodes; in get_reduce_opcode()
175 case ior64: return aco_opcode::num_opcodes; in get_reduce_opcode()
176 case ixor64: return aco_opcode::num_opcodes; in get_reduce_opcode()
177 default: return aco_opcode::num_opcodes; in get_reduce_opcode()
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Daco_optimizer.cpp1497 info->ordered = aco_opcode::num_opcodes; in get_cmp_info()
1498 info->unordered = aco_opcode::num_opcodes; in get_cmp_info()
1499 info->ordered_swapped = aco_opcode::num_opcodes; in get_cmp_info()
1500 info->unordered_swapped = aco_opcode::num_opcodes; in get_cmp_info()
1548 return get_cmp_info(op, &info) ? info.ordered : aco_opcode::num_opcodes; in get_ordered()
1554 return get_cmp_info(op, &info) ? info.unordered : aco_opcode::num_opcodes; in get_unordered()
1560 return get_cmp_info(op, &info) ? info.inverse : aco_opcode::num_opcodes; in get_inverse()
1566 return get_cmp_info(op, &info) ? info.f32 : aco_opcode::num_opcodes; in get_f32_cmp()
1578 return get_cmp_info(op, &info) && info.ordered != aco_opcode::num_opcodes; in is_cmp()
1681 aco_opcode new_op = aco_opcode::num_opcodes; in combine_ordering_test()
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Daco_instruction_selection.cpp928 …_opcode v64_op, aco_opcode s32_op = aco_opcode::num_opcodes, aco_opcode s64_op = aco_opcode::num_o… in emit_comparison()
930 …bit_size == 64 ? s64_op : instr->src[0].src.ssa->bit_size == 32 ? s32_op : aco_opcode::num_opcodes; in emit_comparison()
932 bool use_valu = s_op == aco_opcode::num_opcodes || in emit_comparison()
937 assert(op != aco_opcode::num_opcodes); in emit_comparison()
2905 … ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_eq_u64 : aco_opcode::num_opcodes); in visit_alu_instr()
2913 … ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::num_opcodes); in visit_alu_instr()
3681 opcodes[write_count] = aco_opcode::num_opcodes; in store_lds()
3693 aco_opcode op = aco_opcode::num_opcodes; in store_lds()
3729 if (op == aco_opcode::num_opcodes) in store_lds()
3739 opcodes[second] = aco_opcode::num_opcodes; in store_lds()
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/external/mesa3d/src/broadcom/qpu/
Dqpu_pack.c580 lookup_opcode(const struct opcode_desc *opcodes, size_t num_opcodes, in lookup_opcode() argument
583 for (int i = 0; i < num_opcodes; i++) { in lookup_opcode()
/external/mesa3d/docs/relnotes/
D20.2.0.rst3827 - aco: use num_opcodes instead of last_opcode