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Searched refs:opsel (Results 1 – 14 of 14) sorted by relevance

/external/mesa3d/src/amd/compiler/
Daco_print_ir.cpp594 if (vop3->opsel & (1 << 3)) in print_instr_format_specific()
683 bool *const opsel = (bool *)alloca(instr->operands.size() * sizeof(bool)); in aco_print_instr() local
690 opsel[i] = vop3->opsel & (1 << i); in aco_print_instr()
698 opsel[i] = false; in aco_print_instr()
706 opsel[i] = false; in aco_print_instr()
713 opsel[i] = false; in aco_print_instr()
727 if (opsel[i]) in aco_print_instr()
732 if (opsel[i] || (sel[i] & sdwa_sext)) in aco_print_instr()
Daco_optimizer.cpp1338 vop3->omod != 0 || vop3->opsel != 0) in label_instruction()
1630 uint8_t opsel = 0; in combine_ordering_test() local
1652 …p3->neg[0] != vop3->neg[1] || vop3->abs[0] != vop3->abs[1] || vop3->opsel == 1 || vop3->opsel == 2) in combine_ordering_test()
1656 opsel |= (vop3->opsel & 1) << i; in combine_ordering_test()
1694 if (neg[0] || neg[1] || abs[0] || abs[1] || opsel || num_sgprs > 1) { in combine_ordering_test()
1700 vop3->opsel = opsel; in combine_ordering_test()
1772 new_vop3->opsel = cmp_vop3->opsel; in combine_comparison_ordering()
1855 …p3->neg[0] != vop3->neg[1] || vop3->abs[0] != vop3->abs[1] || vop3->opsel == 1 || vop3->opsel == 2) in combine_constant_comparison_ordering()
1891 new_vop3->opsel = cmp_vop3->opsel; in combine_constant_comparison_ordering()
1940 new_vop3->opsel = cmp_vop3->opsel; in combine_inverse_comparison()
[all …]
Daco_opt_value_numbering.cpp190 a3->opsel == b3->opsel; in operator ()()
Daco_validate.cpp196 …check(vop3->opsel == 0 || program->chip_class >= GFX9, "Opsel is only supported on GFX9+", instr.g… in validate_ir()
201 check((vop3->opsel & (1 << i)) == 0, "Unexpected opsel for operand", instr.get()); in validate_ir()
204 … check((vop3->opsel & (1 << 3)) == 0, "Unexpected opsel for sub-dword definition", instr.get()); in validate_ir()
Daco_lower_to_hw_instr.cpp649 static_cast<VOP3A_instruction*>(perm)->opsel = 1; /* FI (Fetch Inactive) */ in emit_reduction()
760 static_cast<VOP3A_instruction*>(perm)->opsel = 1; /* FI (Fetch Inactive) */ in emit_reduction()
1049 static_cast<VOP3A_instruction*>(instr)->opsel = 0; in copy_constant()
1054 static_cast<VOP3A_instruction*>(instr)->opsel = 2; in copy_constant()
1236 … static_cast<VOP3A_instruction*>(instr)->opsel = hi.physReg().byte() | (lo.physReg().byte() >> 1); in do_pack_2x16()
Daco_ir.h1037 uint8_t opsel : 4; member
1364 return vop3->opsel || vop3->clamp || vop3->omod; in usesModifiers()
Daco_assembler.cpp581 encoding |= vop3->opsel << 11; in emit_instruction()
Daco_register_allocation.cpp401 vop3->opsel |= (byte / 2) << idx; in add_subdword_operand()
505 vop3->opsel |= (1 << 3); /* dst in high half */ in add_subdword_definition()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DVOP3PInstructions.td19 // VOP3 neg/abs and VOP3P opsel/opsel_hi modifiers are allowed.
DVOP3Instructions.td808 // FIXME-GFX10-OPSEL: Need to add "selective" opsel support to some of these
/external/mesa3d/docs/relnotes/
D20.2.0.rst3844 - aco: allow GFX9 partial writes with instructions which use opsel
3848 - aco: fix sub-dword opsel/sdwa checks
3849 - aco: fix validation of opsel when set for the definition
D19.3.0.rst2822 - aco: Assemble opsel in VOP3 instructions.
D20.1.0.rst3550 - aco: print and validate opsel
D20.3.0.rst4112 - aco: don't allow destination opsel for v_cvt_pknorm