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/external/linux-kselftest/tools/testing/selftests/powerpc/pmu/ebb/
Debb_handler.S143 SAVE_VSR(0, r3)
148 SAVE_VSR(1, r3)
149 SAVE_VSR(2, r3)
150 SAVE_VSR(3, r3)
151 SAVE_VSR(4, r3)
152 SAVE_VSR(5, r3)
153 SAVE_VSR(6, r3)
154 SAVE_VSR(7, r3)
155 SAVE_VSR(8, r3)
156 SAVE_VSR(9, r3)
[all …]
/external/compiler-rt/lib/tsan/rtl/
Dtsan_rtl_ppc64.S21 std r3,32(r1)
24 addi r3,r1,48
27 xor r4,r3,r4
47 ld r3,32(r1)
57 std r5,0(r3) // mangled stack ptr of caller
59 std r5,8(r3) // caller's saved TOC pointer
61 std r0,16(r3) // caller's mangled return address
64 std r14,24(r3)
65 stfd f14,176(r3)
66 stw r0,172(r3) // CR
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/src/arm/
Dtrampoline.S34 stmfd sp!, {r0-r3}
47 stmfd sp!, {r0-r3}
60 stmfd sp!, {r0-r3}
73 stmfd sp!, {r0-r3}
86 stmfd sp!, {r0-r3}
99 stmfd sp!, {r0-r3}
112 stmfd sp!, {r0-r3}
125 stmfd sp!, {r0-r3}
138 stmfd sp!, {r0-r3}
151 stmfd sp!, {r0-r3}
[all …]
/external/libffi/src/arm/
Dtrampoline.S34 stmfd sp!, {r0-r3}
47 stmfd sp!, {r0-r3}
60 stmfd sp!, {r0-r3}
73 stmfd sp!, {r0-r3}
86 stmfd sp!, {r0-r3}
99 stmfd sp!, {r0-r3}
112 stmfd sp!, {r0-r3}
125 stmfd sp!, {r0-r3}
138 stmfd sp!, {r0-r3}
151 stmfd sp!, {r0-r3}
[all …]
/external/libxaac/decoder/armv7/
Dixheaacd_mps_complex_fft_64_asm.s58 STMIA r3!, {r4-r11}
65 SUB r3, r3, r0, LSL #3
67 STR r3, [sp, #0x50]
132 LDR r3, [sp, #0x50]
134 ADD r12, r3, #8
136 MOV r3, r1, ASR #2
137 ADD r3, r3, r1, ASR #3
138 SUB r3, r3, r1, ASR #4
139 ADD r3, r3, r1, ASR #5
140 SUB r3, r3, r1, ASR #6
[all …]
Dixheaacd_complex_ifft_p2.s73 STMIA r3!, {r4-r11}
80 SUB r3, r3, r0, LSL #3
82 STR r3, [sp, #0x50]
147 LDR r3, [sp, #0x50]
149 ADD r12, r3, #8
151 MOV r3, r1, ASR #2
152 ADD r3, r3, r1, ASR #3
153 SUB r3, r3, r1, ASR #4
154 ADD r3, r3, r1, ASR #5
155 SUB r3, r3, r1, ASR #6
[all …]
Dixheaacd_complex_fft_p2.s73 STMIA r3!, {r4-r11}
80 SUB r3, r3, r0, LSL #3
82 STR r3, [sp, #0x50]
147 LDR r3, [sp, #0x50]
149 ADD r12, r3, #8
151 MOV r3, r1, ASR #2
152 ADD r3, r3, r1, ASR #3
153 SUB r3, r3, r1, ASR #4
154 ADD r3, r3, r1, ASR #5
155 SUB r3, r3, r1, ASR #6
[all …]
Dixheaacd_fwd_modulation.s30 STMFD sp!, {r3-r9, r12, lr}
35 LDR r1, [r3]
41 MOV r6, r3
43 LDR r3, [r0], #4
46 MOV r3, r3, ASR #4
49 QSUB r9, r3, r12
50 ADD r3, r3, r12
54 STR r3, [r7], #4
63 MOV r3, #0xd8
64 LSL r3, r3, #4
[all …]
/external/capstone/suite/MC/ARM/
Dbasic-thumb-instructions.s.cs6 0xd1,0x18 = adds r1, r2, r3
15 0x9d,0x44 = add sp, r3
19 0xff,0xa3 = adr r3, #1020
20 0x1a,0x10 = asrs r2, r3, #32
21 0x5a,0x11 = asrs r2, r3, #5
22 0x5a,0x10 = asrs r2, r3, #1
25 0x6b,0x15 = asrs r3, r5, #21
40 0xa3,0x42 = cmp r3, r4
45 0xff,0xcb = ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7}
46 0xba,0xca = ldm r2!, {r1, r3, r4, r5, r7}
[all …]
Darm-memory-instructions.s.cs3 0x3f,0x60,0x93,0xe5 = ldr r6, [r3, #63]
6 0x1e,0x30,0x11,0xe4 = ldr r3, [r1], #-30
8 0x01,0x30,0x98,0xe7 = ldr r3, [r8, r1]
9 0x03,0x20,0x15,0xe7 = ldr r2, [r5, -r3]
14 0x06,0x40,0x13,0xe6 = ldr r4, [r3], -r6
15 0x82,0x37,0x18,0xe7 = ldr r3, [r8, -r2, lsl #15]
16 0xc3,0x17,0x95,0xe6 = ldr r1, [r5], r3, asr #15
17 0x00,0x30,0xd8,0xe5 = ldrb r3, [r8]
19 0xff,0x9f,0xf3,0xe5 = ldrb r9, [r3, #4095]!
24 0x02,0x30,0xf5,0xe7 = ldrb r3, [r5, r2]!
[all …]
/external/virglrenderer/src/mesa/util/
Du_math.c144 float *r0, *r1, *r2, *r3; in util_invert_mat4x4() local
154 r0 = wtmp[0], r1 = wtmp[1], r2 = wtmp[2], r3 = wtmp[3]; in util_invert_mat4x4()
165 r3[0] = MAT(m, 3, 0), r3[1] = MAT(m, 3, 1), r3[2] = MAT(m, 3, 2), r3[3] = MAT(m, 3, 3), in util_invert_mat4x4()
166 r3[7] = 1.0, r3[4] = r3[5] = r3[6] = 0.0; in util_invert_mat4x4()
169 if (fabsf(r3[0]) > fabsf(r2[0])) in util_invert_mat4x4()
170 SWAP_ROWS(r3, r2); in util_invert_mat4x4()
181 m3 = r3[0] / r0[0]; in util_invert_mat4x4()
185 r3[1] -= m3 * s; in util_invert_mat4x4()
189 r3[2] -= m3 * s; in util_invert_mat4x4()
193 r3[3] -= m3 * s; in util_invert_mat4x4()
[all …]
/external/musl/src/string/arm/
Dmemcpy.S69 rsb r3, r1, #0
70 ands r3, r3, #3
77 movs r12, r3, lsl #31
78 sub r2, r2, r3 /* we know that r3 <= r2 because r2 >= 4 */
79 ldrbmi r3, [r1], #1
82 strbmi r3, [r0], #1
99 rsb r3, r0, #0
100 ands r3, r3, #0x1C
102 cmp r3, r2
103 andhi r3, r2, #0x1C
[all …]
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-rn-operand-rm-all-low-in-it-block-t32.cc98 {{gt, r3, r1, r0}, true, gt, "gt r3 r1 r0", "gt_r3_r1_r0"},
99 {{ls, r4, r3, r6}, true, ls, "ls r4 r3 r6", "ls_r4_r3_r6"},
100 {{pl, r5, r3, r4}, true, pl, "pl r5 r3 r4", "pl_r5_r3_r4"},
102 {{ls, r1, r2, r3}, true, ls, "ls r1 r2 r3", "ls_r1_r2_r3"},
103 {{vc, r4, r3, r4}, true, vc, "vc r4 r3 r4", "vc_r4_r3_r4"},
105 {{ls, r3, r4, r0}, true, ls, "ls r3 r4 r0", "ls_r3_r4_r0"},
106 {{gt, r6, r4, r3}, true, gt, "gt r6 r4 r3", "gt_r6_r4_r3"},
113 {{lt, r4, r3, r3}, true, lt, "lt r4 r3 r3", "lt_r4_r3_r3"},
115 {{ls, r3, r3, r1}, true, ls, "ls r3 r3 r1", "ls_r3_r3_r1"},
118 {{eq, r4, r3, r0}, true, eq, "eq r4 r3 r0", "eq_r4_r3_r0"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-rmlow-in-it-block-t32.cc98 {{eq, r0, r3, r0}, true, eq, "eq r0 r3 r0", "eq_r0_r3_r0"},
106 {{eq, r1, r3, r1}, true, eq, "eq r1 r3 r1", "eq_r1_r3_r1"},
114 {{eq, r2, r3, r2}, true, eq, "eq r2 r3 r2", "eq_r2_r3_r2"},
119 {{eq, r3, r0, r3}, true, eq, "eq r3 r0 r3", "eq_r3_r0_r3"},
120 {{eq, r3, r1, r3}, true, eq, "eq r3 r1 r3", "eq_r3_r1_r3"},
121 {{eq, r3, r2, r3}, true, eq, "eq r3 r2 r3", "eq_r3_r2_r3"},
122 {{eq, r3, r3, r3}, true, eq, "eq r3 r3 r3", "eq_r3_r3_r3"},
123 {{eq, r3, r4, r3}, true, eq, "eq r3 r4 r3", "eq_r3_r4_r3"},
124 {{eq, r3, r5, r3}, true, eq, "eq r3 r5 r3", "eq_r3_r5_r3"},
125 {{eq, r3, r6, r3}, true, eq, "eq r3 r6 r3", "eq_r3_r6_r3"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-t32.cc105 {{{gt, r3, r3, r0}, true, gt, "gt r3 r3 r0", "gt_r3_r3_r0"},
112 {{hi, r6, r6, r3}, true, hi, "hi r6 r6 r3", "hi_r6_r6_r3"},
117 {{cc, r4, r4, r3}, true, cc, "cc r4 r4 r3", "cc_r4_r4_r3"},
118 {{mi, r5, r5, r3}, true, mi, "mi r5 r5 r3", "mi_r5_r5_r3"},
119 {{cs, r3, r3, r0}, true, cs, "cs r3 r3 r0", "cs_r3_r3_r0"},
122 {{cc, r3, r3, r6}, true, cc, "cc r3 r3 r6", "cc_r3_r3_r6"},
123 {{hi, r7, r7, r3}, true, hi, "hi r7 r7 r3", "hi_r7_r7_r3"},
126 {{le, r5, r5, r3}, true, le, "le r5 r5 r3", "le_r5_r5_r3"},
128 {{vs, r7, r7, r3}, true, vs, "vs r7 r7 r3", "vs_r7_r7_r3"},
129 {{cc, r0, r0, r3}, true, cc, "cc r0 r0 r3", "cc_r0_r0_r3"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-t32.cc97 {{{mi, r3, r3, 90}, true, mi, "mi r3 r3 90", "mi_r3_r3_90"},
106 {{gt, r3, r3, 0}, true, gt, "gt r3 r3 0", "gt_r3_r3_0"},
113 {{lt, r3, r3, 207}, true, lt, "lt r3 r3 207", "lt_r3_r3_207"},
114 {{vs, r3, r3, 101}, true, vs, "vs r3 r3 101", "vs_r3_r3_101"},
121 {{hi, r3, r3, 62}, true, hi, "hi r3 r3 62", "hi_r3_r3_62"},
122 {{eq, r3, r3, 216}, true, eq, "eq r3 r3 216", "eq_r3_r3_216"},
135 {{ls, r3, r3, 114}, true, ls, "ls r3 r3 114", "ls_r3_r3_114"},
139 {{hi, r3, r3, 17}, true, hi, "hi r3 r3 17", "hi_r3_r3_17"},
141 {{hi, r3, r3, 20}, true, hi, "hi r3 r3 20", "hi_r3_r3_20"},
143 {{eq, r3, r3, 172}, true, eq, "eq r3 r3 172", "eq_r3_r3_172"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm8-t32.cc865 {{al, r3, r3, 0}, false, al, "al r3 r3 0", "al_r3_r3_0"},
866 {{al, r3, r3, 1}, false, al, "al r3 r3 1", "al_r3_r3_1"},
867 {{al, r3, r3, 2}, false, al, "al r3 r3 2", "al_r3_r3_2"},
868 {{al, r3, r3, 3}, false, al, "al r3 r3 3", "al_r3_r3_3"},
869 {{al, r3, r3, 4}, false, al, "al r3 r3 4", "al_r3_r3_4"},
870 {{al, r3, r3, 5}, false, al, "al r3 r3 5", "al_r3_r3_5"},
871 {{al, r3, r3, 6}, false, al, "al r3 r3 6", "al_r3_r3_6"},
872 {{al, r3, r3, 7}, false, al, "al r3 r3 7", "al_r3_r3_7"},
873 {{al, r3, r3, 8}, false, al, "al r3 r3 8", "al_r3_r3_8"},
874 {{al, r3, r3, 9}, false, al, "al r3 r3 9", "al_r3_r3_9"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc99 {{pl, r3, r3, ROR, r3}, true, pl, "pl r3 r3 ROR r3", "pl_r3_r3_ROR_r3"},
105 {{le, r3, r3, ASR, r6}, true, le, "le r3 r3 ASR r6", "le_r3_r3_ASR_r6"},
107 {{pl, r3, r3, ASR, r2}, true, pl, "pl r3 r3 ASR r2", "pl_r3_r3_ASR_r2"},
113 {{ls, r6, r6, LSL, r3}, true, ls, "ls r6 r6 LSL r3", "ls_r6_r6_LSL_r3"},
122 {{ge, r6, r6, ROR, r3}, true, ge, "ge r6 r6 ROR r3", "ge_r6_r6_ROR_r3"},
123 {{cs, r7, r7, ASR, r3}, true, cs, "cs r7 r7 ASR r3", "cs_r7_r7_ASR_r3"},
124 {{ne, r3, r3, ROR, r4}, true, ne, "ne r3 r3 ROR r4", "ne_r3_r3_ROR_r4"},
134 {{vc, r5, r5, ROR, r3}, true, vc, "vc r5 r5 ROR r3", "vc_r5_r5_ROR_r3"},
135 {{ls, r3, r3, LSL, r2}, true, ls, "ls r3 r3 LSL r2", "ls_r3_r3_LSL_r2"},
136 {{ls, r6, r6, ASR, r3}, true, ls, "ls r6 r6 ASR r3", "ls_r6_r6_ASR_r3"},
[all …]
Dtest-assembler-cond-rd-operand-rn-low-registers-in-it-block-t32.cc98 {{eq, r0, r3}, true, eq, "eq r0 r3", "eq_r0_r3"},
106 {{eq, r1, r3}, true, eq, "eq r1 r3", "eq_r1_r3"},
114 {{eq, r2, r3}, true, eq, "eq r2 r3", "eq_r2_r3"},
119 {{eq, r3, r0}, true, eq, "eq r3 r0", "eq_r3_r0"},
120 {{eq, r3, r1}, true, eq, "eq r3 r1", "eq_r3_r1"},
121 {{eq, r3, r2}, true, eq, "eq r3 r2", "eq_r3_r2"},
122 {{eq, r3, r3}, true, eq, "eq r3 r3", "eq_r3_r3"},
123 {{eq, r3, r4}, true, eq, "eq r3 r4", "eq_r3_r4"},
124 {{eq, r3, r5}, true, eq, "eq r3 r5", "eq_r3_r5"},
125 {{eq, r3, r6}, true, eq, "eq r3 r6", "eq_r3_r6"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-zero-in-it-block-t32.cc98 {{eq, r0, r3, 0}, true, eq, "eq r0 r3 0", "eq_r0_r3_0"},
106 {{eq, r1, r3, 0}, true, eq, "eq r1 r3 0", "eq_r1_r3_0"},
114 {{eq, r2, r3, 0}, true, eq, "eq r2 r3 0", "eq_r2_r3_0"},
119 {{eq, r3, r0, 0}, true, eq, "eq r3 r0 0", "eq_r3_r0_0"},
120 {{eq, r3, r1, 0}, true, eq, "eq r3 r1 0", "eq_r3_r1_0"},
121 {{eq, r3, r2, 0}, true, eq, "eq r3 r2 0", "eq_r3_r2_0"},
122 {{eq, r3, r3, 0}, true, eq, "eq r3 r3 0", "eq_r3_r3_0"},
123 {{eq, r3, r4, 0}, true, eq, "eq r3 r4 0", "eq_r3_r4_0"},
124 {{eq, r3, r5, 0}, true, eq, "eq r3 r5 0", "eq_r3_r5_0"},
125 {{eq, r3, r6, 0}, true, eq, "eq r3 r6 0", "eq_r3_r6_0"},
[all …]
/external/llvm/test/MC/ARM/
Darm-arithmetic-aliases.s8 sub r2, r2, r3
9 sub r2, r3
13 @ CHECK: sub r2, r2, r3 @ encoding: [0x03,0x20,0x42,0xe0]
14 @ CHECK: sub r2, r2, r3 @ encoding: [0x03,0x20,0x42,0xe0]
18 add r2, r2, r3
19 add r2, r3
23 @ CHECK: add r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe0]
24 @ CHECK: add r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe0]
28 and r2, r2, r3
29 and r2, r3
[all …]
/external/linux-kselftest/tools/testing/selftests/powerpc/tm/
Dtm-signal.S29 std r3, STACK_FRAME_PARAM(0)(sp) /* pid */
35 ld r3, STACK_FRAME_PARAM(1)(sp)
36 cmpdi r3, 0
40 ld r3, STACK_FRAME_PARAM(2)(sp)
41 cmpdi r3, 0
45 ld r3, STACK_FRAME_PARAM(3)(sp)
46 cmpdi r3, 0
50 ld r3, STACK_FRAME_PARAM(4)(sp)
51 cmpdi r3, 0
60 ld r3, STACK_FRAME_PARAM(0)(sp)
[all …]
/external/vixl/benchmarks/aarch32/
Dasm-disasm-speed-test.cc206 __ movs(Narrow, r3, 0U); in Generate_1()
220 __ strb(Narrow, r3, MemOperand(r4, 24)); in Generate_1()
221 __ str(Narrow, r3, MemOperand(r4, 28)); in Generate_1()
222 __ strb(r3, MemOperand(r4, 32)); in Generate_1()
223 __ strb(r3, MemOperand(r4, 36)); in Generate_1()
224 __ str(Narrow, r3, MemOperand(r4, 52)); in Generate_1()
225 __ str(Narrow, r3, MemOperand(r4, 56)); in Generate_1()
226 __ str(Narrow, r3, MemOperand(r4, 60)); in Generate_1()
227 __ str(Narrow, r3, MemOperand(r4, 68)); in Generate_1()
228 __ str(Narrow, r3, MemOperand(r4, 72)); in Generate_1()
[all …]
/external/libhevc/common/arm/
Dihevc_intra_pred_chroma_horz.s85 @r3 => dst_strd
130 vst1.16 {q1},[r2],r3 @store in 1st row 0-16 columns
131 vst1.16 {q1},[r9],r3 @store in 1st row 16-32 columns
134 vst1.16 {q2},[r2],r3
135 vst1.16 {q2},[r9],r3
138 vst1.16 {q3},[r2],r3
139 vst1.16 {q3},[r9],r3
142 vst1.16 {q4},[r2],r3
143 vst1.16 {q4},[r9],r3
146 vst1.16 {q1},[r2],r3
[all …]
Dihevc_intra_pred_luma_horz.s85 @r3 => dst_strd
126 vst1.8 {q1},[r2],r3 @store in 1st row 0-16 columns
127 vst1.8 {q1},[r9],r3 @store in 1st row 16-32 columns
130 vst1.8 {q2},[r2],r3
131 vst1.8 {q2},[r9],r3
134 vst1.8 {q3},[r2],r3
135 vst1.8 {q3},[r9],r3
138 vst1.8 {q4},[r2],r3
139 vst1.8 {q4},[r9],r3
142 vst1.8 {q1},[r2],r3
[all …]

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