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Searched refs:radeon_set_sh_reg_seq (Results 1 – 10 of 10) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_compute.c352 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2); in si_emit_initial_compute_regs()
374 radeon_set_sh_reg_seq(cs, R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2); in si_emit_initial_compute_regs()
508 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2); in si_switch_compute_shader()
512 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2); in si_switch_compute_shader()
565 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 4); in setup_scratch_rsrc_user_sgprs()
626 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 2); in si_setup_user_sgprs_co_v2()
636 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 2); in si_setup_user_sgprs_co_v2()
644 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 1); in si_setup_user_sgprs_co_v2()
704 radeon_set_sh_reg_seq(cs, grid_size_reg, 3); in si_setup_nir_user_data()
712 radeon_set_sh_reg_seq(cs, block_size_reg, 3); in si_setup_nir_user_data()
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Dsi_build_pm4.h90 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq() function
101 radeon_set_sh_reg_seq(cs, reg, 1); in radeon_set_sh_reg()
Dsi_compute_prim_discard.c1220 radeon_set_sh_reg_seq(cs, R_00B820_COMPUTE_NUM_THREAD_Y, 2); in si_dispatch_prim_discard_cs_and_draw()
1224 radeon_set_sh_reg_seq(cs, R_00B814_COMPUTE_START_Y, 2); in si_dispatch_prim_discard_cs_and_draw()
1374 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2); in si_dispatch_prim_discard_cs_and_draw()
1378 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2); in si_dispatch_prim_discard_cs_and_draw()
1462 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, user_sgprs); in si_dispatch_prim_discard_cs_and_draw()
1484 radeon_set_sh_reg_seq(cs, R_00B904_COMPUTE_USER_DATA_1, 3); in si_dispatch_prim_discard_cs_and_draw()
Dsi_state_draw.c260 radeon_set_sh_reg_seq( in si_emit_derived_tess_state()
275 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2); in si_emit_derived_tess_state()
280 radeon_set_sh_reg_seq( in si_emit_derived_tess_state()
289 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2); in si_emit_derived_tess_state()
925 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4, sctx->num_vs_blit_sgprs); in si_emit_draw_packets()
931 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3); in si_emit_draw_packets()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_cs.h170 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq() function
180 radeon_set_sh_reg_seq(cs, reg, 1); in radeon_set_sh_reg()
/external/mesa3d/src/amd/vulkan/
Dradv_cs.h97 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq() function
108 radeon_set_sh_reg_seq(cs, reg, 1); in radeon_set_sh_reg()
Dradv_pipeline.c4194 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4); in radv_pipeline_generate_hw_vs()
4257 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4); in radv_pipeline_generate_hw_es()
4273 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2); in radv_pipeline_generate_hw_ls()
4282 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2); in radv_pipeline_generate_hw_ls()
4300 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2); in radv_pipeline_generate_hw_ngg()
4303 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2); in radv_pipeline_generate_hw_ngg()
4431 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2); in radv_pipeline_generate_hw_hs()
4435 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2); in radv_pipeline_generate_hw_hs()
4440 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2); in radv_pipeline_generate_hw_hs()
4444 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4); in radv_pipeline_generate_hw_hs()
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Dsi_cmd_buffer.c84 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3); in si_emit_compute()
89 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2); in si_emit_compute()
97 radeon_set_sh_reg_seq(cs, in si_emit_compute()
Dradv_cmd_buffer.c946 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count); in radv_emit_inline_push_consts()
5183 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr, in radv_emit_draw_packets()
5686 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3); in radv_emit_dispatch_packets()
5703 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + in radv_emit_dispatch_packets()
5711 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3); in radv_emit_dispatch_packets()
Dradv_device.c3458 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2); in radv_emit_compute_scratch()
3546 radeon_set_sh_reg_seq(cs, regs[i], 4); in radv_emit_trap_handler()
3553 radeon_set_sh_reg_seq(cs, R_00B838_COMPUTE_TBA_LO, 4); in radv_emit_trap_handler()