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Searched refs:radeon_set_uconfig_reg (Results 1 – 13 of 13) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_sqtt.c79 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, in radv_emit_thread_trace_start()
122 radeon_set_uconfig_reg(cs, R_030CDC_SQ_THREAD_TRACE_BASE2, in radv_emit_thread_trace_start()
125 radeon_set_uconfig_reg(cs, R_030CC0_SQ_THREAD_TRACE_BASE, in radv_emit_thread_trace_start()
128 radeon_set_uconfig_reg(cs, R_030CC4_SQ_THREAD_TRACE_SIZE, in radv_emit_thread_trace_start()
131 radeon_set_uconfig_reg(cs, R_030CD4_SQ_THREAD_TRACE_CTRL, in radv_emit_thread_trace_start()
146 radeon_set_uconfig_reg(cs, R_030CC8_SQ_THREAD_TRACE_MASK, in radv_emit_thread_trace_start()
150 radeon_set_uconfig_reg(cs, R_030CCC_SQ_THREAD_TRACE_TOKEN_MASK, in radv_emit_thread_trace_start()
156 radeon_set_uconfig_reg(cs, R_030CD0_SQ_THREAD_TRACE_PERF_MASK, in radv_emit_thread_trace_start()
160 radeon_set_uconfig_reg(cs, R_030CE0_SQ_THREAD_TRACE_TOKEN_MASK2, in radv_emit_thread_trace_start()
163 radeon_set_uconfig_reg(cs, R_030CEC_SQ_THREAD_TRACE_HIWATER, in radv_emit_thread_trace_start()
[all …]
Dsi_cmd_buffer.c59 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
72 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
114 radeon_set_uconfig_reg(cs, R_0301EC_CP_COHER_START_DELAY, in si_emit_compute()
269 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0); in si_emit_graphics()
270 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0); in si_emit_graphics()
271 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0); in si_emit_graphics()
272 radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0); in si_emit_graphics()
273 radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0); in si_emit_graphics()
275 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0); in si_emit_graphics()
276 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0); in si_emit_graphics()
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Dradv_cs.h149 static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_uconfig_reg() function
Dradv_device.c3402 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE, in radv_emit_tess_factor_ring()
3404 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE, in radv_emit_tess_factor_ring()
3408 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD, in radv_emit_tess_factor_ring()
3411 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI, in radv_emit_tess_factor_ring()
3414 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, in radv_emit_tess_factor_ring()
Dradv_pipeline.c4419 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl); in radv_pipeline_generate_hw_ngg()
5029 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, in gfx10_pipeline_generate_ge_cntl()
Dradv_cmd_buffer.c3111 radeon_set_uconfig_reg(cs, in radv_emit_draw_registers()
6678 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0); in radv_flush_vgt_streamout()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_perfcounter.c726 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, value); in si_pc_emit_instance()
795 radeon_set_uconfig_reg(cs, *reg++, selectors[idx] | regs->select_or); in si_pc_emit_select()
797 radeon_set_uconfig_reg(cs, *reg++, 0); in si_pc_emit_select()
838 radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL, in si_pc_emit_start()
842 radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL, in si_pc_emit_start()
860 radeon_set_uconfig_reg( in si_pc_emit_stop()
925 radeon_set_uconfig_reg(sctx->gfx_cs, R_037390_RLC_PERFMON_CLK_CNTL, in si_inhibit_clockgating()
928 radeon_set_uconfig_reg(sctx->gfx_cs, R_0372FC_RLC_PERFMON_CLK_CNTL, in si_inhibit_clockgating()
Dsi_build_pm4.h114 static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_uconfig_reg() function
Dsi_state_shaders.c934 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, value); in gfx10_emit_ge_pc_alloc()
3498 radeon_set_uconfig_reg(cs, R_030900_VGT_ESGS_RING_SIZE, in si_update_gs_ring_buffers()
3502 radeon_set_uconfig_reg(cs, R_030904_VGT_GSVS_RING_SIZE, in si_update_gs_ring_buffers()
3779 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE, in si_init_tess_factor_ring()
3781 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE, factor_va >> 8); in si_init_tess_factor_ring()
3783 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD, in si_init_tess_factor_ring()
3786 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI, in si_init_tess_factor_ring()
3789 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, in si_init_tess_factor_ring()
Dsi_state_streamout.c281 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0); in si_flush_vgt_streamout()
Dsi_state_draw.c715 radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, ge_cntl); in gfx10_emit_ge_cntl()
737 radeon_set_uconfig_reg(cs, R_030908_VGT_PRIMITIVE_TYPE, vgt_prim); in si_emit_draw_registers()
749 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN, primitive_restart); in si_emit_draw_registers()
Dsi_compute.c395 radeon_set_uconfig_reg(cs, R_0301EC_CP_COHER_START_DELAY, in si_emit_initial_compute_regs()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_cs.h192 static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_uconfig_reg() function