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Searched refs:regid (Results 1 – 25 of 37) sorted by relevance

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/external/mesa3d/src/freedreno/ir3/
Dir3_shader.c73 if (v->inputs[i].regid >= regid(48,0)) in fixup_regfootprint()
78 int32_t regid = v->inputs[i].regid + n; in fixup_regfootprint() local
81 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2); in fixup_regfootprint()
83 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3); in fixup_regfootprint()
86 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2); in fixup_regfootprint()
93 if (!VALIDREG(v->outputs[i].regid)) in fixup_regfootprint()
95 int32_t regid = v->outputs[i].regid + 3; in fixup_regfootprint() local
98 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2); in fixup_regfootprint()
100 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3); in fixup_regfootprint()
103 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2); in fixup_regfootprint()
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Dir3_shader.h568 uint8_t regid; member
592 uint8_t regid; member
862 uint8_t regid; member
887 if (regid_ != regid(63, 0)) { in ir3_link_add()
891 l->var[i].regid = regid_; in ir3_link_add()
911 const unsigned default_regid = pack_vs_out ? regid(63, 0) : regid(0, 0); in ir3_link_shaders()
945 ir3_link_add(l, k >= 0 ? vs->outputs[k].regid : default_regid, in ir3_link_shaders()
956 uint32_t regid = so->outputs[j].regid; in ir3_find_output_regid() local
958 regid |= HALF_REG_ID; in ir3_find_output_regid()
959 return regid; in ir3_find_output_regid()
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Dir3_ra.c1304 unsigned regid = instr->regs[0]->num; in assign_arr_base() local
1311 regid *= 2; in assign_arr_base()
1330 regid, regid + reglen)) { in assign_arr_base()
1331 base = MAX2(base, regid + reglen); in assign_arr_base()
1379 unsigned regid = instr->regs[0]->num; in ra_precolor() local
1380 ra_assert(ctx, regid >= id->off); in ra_precolor()
1381 regid -= id->off; in ra_precolor()
1383 unsigned reg = ctx->set->gpr_to_ra_reg[id->cls][regid]; in ra_precolor()
1435 unsigned regid = instr->regs[0]->num + i; in precolor() local
1438 regid -= FIRST_HIGH_REG; in precolor()
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Dir3_legalize.c198 if (last_rel && (reg->num == regid(REG_A0, 0))) { in legalize_block()
301 ir3_reg_create(baryf, regid(63, 0), 0); in legalize_block()
303 ir3_reg_create(baryf, regid(0, 0), 0); in legalize_block()
327 ir3_reg_create(baryf, regid(63, 0), 0)->flags |= IR3_REG_EI; in legalize_block()
329 ir3_reg_create(baryf, regid(0, 0), 0); in legalize_block()
Dir3_compiler_nir.c96 unsigned r = regid(n + dp / 4, dp % 4); in create_driver_param()
757 unsigned ubo = regid(const_state->offsets.ubo, 0); in emit_intrinsic_load_ubo()
856 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) + in emit_intrinsic_ssbo_size()
1237 unsigned cb = regid(const_state->offsets.image_dims, 0) + in emit_intrinsic_image_size_tex()
1897 cond->regs[0]->num = regid(REG_P0, 0); in emit_intrinsic()
1901 kill->regs[1]->num = regid(REG_P0, 0); in emit_intrinsic()
1921 cond->regs[0]->num = regid(REG_P0, 0); in emit_intrinsic()
2798 cond->regs[0]->num = regid(REG_P0, 0); in emit_stream_out()
2823 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i)); in emit_stream_out()
2839 out = ctx->outputs[regid(strmout->output[i].register_index, c)]; in emit_stream_out()
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Dir3_context.c459 instr->regs[0]->num = regid(REG_A0, 0); in create_addr0()
471 instr->regs[0]->num = regid(REG_A0, 1); in create_addr1()
534 cond->regs[0]->num = regid(REG_P0, 0); in ir3_get_predicate()
Dir3_cp_postsched.c66 (instr->regs[0]->num == regid(REG_A0, 0))) in has_conflicting_write()
Dir3.h709 if (dst->num == regid(REG_P0, 0)) in is_same_type_mov()
918 (reg->num == regid(REG_P0, 0))) in writes_gpr()
927 return dst->num == regid(REG_A0, 0); in writes_addr0()
936 return dst->num == regid(REG_A0, 1); in writes_addr1()
/external/mesa3d/src/gallium/drivers/freedreno/a6xx/
Dfd6_const.c38 const struct ir3_shader_variant *v, uint32_t regid, in fd6_emit_const_user() argument
41 emit_const_asserts(ring, v, regid, sizedwords); in fd6_emit_const_user()
52 .dst_off = regid/4, in fd6_emit_const_user()
64 .dst_off = regid/4, in fd6_emit_const_user()
77 const struct ir3_shader_variant *v, uint32_t regid, in fd6_emit_const_bo() argument
80 uint32_t dst_off = regid / 4; in fd6_emit_const_bo()
85 emit_const_asserts(ring, v, regid, sizedwords); in fd6_emit_const_bo()
137 const unsigned regid = const_state->offsets.primitive_param * 4 + 4; in emit_tess_bos() local
141 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid / 4) | in emit_tess_bos()
154 const unsigned regid = const_state->offsets.primitive_param; in emit_stage_tess_consts() local
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Dfd6_program.c140 if (l->var[idx].regid == v->outputs[k].regid) in link_stream_out()
147 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc); in link_stream_out()
188 if (l->var[idx].regid == v->outputs[k].regid) in setup_stream_out()
310 return regid(63,0); in next_regid()
368 tess_coord_x_regid = regid(63, 0); in setup_stateobj()
369 tess_coord_y_regid = regid(63, 0); in setup_stateobj()
370 hs_patch_regid = regid(63, 0); in setup_stateobj()
371 ds_patch_regid = regid(63, 0); in setup_stateobj()
372 hs_invocation_regid = regid(63, 0); in setup_stateobj()
384 gs_header_regid = regid(63, 0); in setup_stateobj()
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Dfd6_compute.c122 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) | in cs_program_emit()
123 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) | in cs_program_emit()
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/
Dfd3_emit.c62 uint32_t regid, uint32_t sizedwords, const uint32_t *dwords) in fd3_emit_const_user() argument
64 emit_const_asserts(ring, v, regid, sizedwords); in fd3_emit_const_user()
67 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) | in fd3_emit_const_user()
79 uint32_t regid, uint32_t offset, uint32_t sizedwords, in fd3_emit_const_bo() argument
82 uint32_t dst_off = regid / 2; in fd3_emit_const_bo()
91 emit_const_asserts(ring, v, regid, sizedwords); in fd3_emit_const_bo()
104 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets) in fd3_emit_const_ptrs() argument
109 debug_assert((regid % 4) == 0); in fd3_emit_const_ptrs()
112 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) | in fd3_emit_const_ptrs()
384 unsigned vertex_regid = regid(63, 0); in fd3_emit_vertex_bufs()
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Dfd3_program.c176 zwcoord_regid = (coord_regid == regid(63,0)) ? regid(63,0) : (coord_regid + 2); in fd3_program_emit()
254 reg |= A3XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid); in fd3_program_emit()
258 reg |= A3XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid); in fd3_program_emit()
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/
Dfd4_emit.c56 const struct ir3_shader_variant *v, uint32_t regid, uint32_t sizedwords, in fd4_emit_const_user() argument
59 emit_const_asserts(ring, v, regid, sizedwords); in fd4_emit_const_user()
62 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) | in fd4_emit_const_user()
74 uint32_t regid, uint32_t offset, uint32_t sizedwords, in fd4_emit_const_bo() argument
77 uint32_t dst_off = regid / 4; in fd4_emit_const_bo()
82 emit_const_asserts(ring, v, regid, sizedwords); in fd4_emit_const_bo()
95 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets) in fd4_emit_const_ptrs() argument
100 debug_assert((regid % 4) == 0); in fd4_emit_const_ptrs()
103 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) | in fd4_emit_const_ptrs()
384 unsigned vertex_regid = regid(63, 0); in fd4_emit_vertex_bufs()
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Dfd4_program.c185 if (pos_regid == regid(63, 0)) { in fd4_program_emit()
190 pos_regid = regid(0, 0); in fd4_program_emit()
211 zwcoord_regid = (coord_regid == regid(63,0)) ? regid(63,0) : (coord_regid + 2); in fd4_program_emit()
304 reg |= A4XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid); in fd4_program_emit()
308 reg |= A4XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid); in fd4_program_emit()
/external/mesa3d/src/gallium/drivers/freedreno/a5xx/
Dfd5_program.c112 if (l->var[idx].regid == v->outputs[k].regid) in link_stream_out()
119 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc); in link_stream_out()
156 if (l->var[idx].regid == v->outputs[k].regid) in emit_stream_out()
323 zwcoord_regid = (coord_regid == regid(63,0)) ? regid(63,0) : (coord_regid + 2); in fd5_program_emit()
428 if (pos_regid != regid(63,0)) in fd5_program_emit()
431 if (psize_regid != regid(63,0)) { in fd5_program_emit()
452 reg |= A5XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid); in fd5_program_emit()
456 reg |= A5XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid); in fd5_program_emit()
566 COND(samp_mask_regid != regid(63, 0), in fd5_program_emit()
569 COND(samp_id_regid != regid(63, 0), in fd5_program_emit()
Dfd5_emit.c59 const struct ir3_shader_variant *v, uint32_t regid, uint32_t sizedwords, in fd5_emit_const_user() argument
62 emit_const_asserts(ring, v, regid, sizedwords); in fd5_emit_const_user()
65 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) | in fd5_emit_const_user()
78 uint32_t regid, uint32_t offset, uint32_t sizedwords, struct fd_bo *bo) in fd5_emit_const_bo() argument
80 uint32_t dst_off = regid / 4; in fd5_emit_const_bo()
85 emit_const_asserts(ring, v, regid, sizedwords); in fd5_emit_const_bo()
98 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets) in fd5_emit_const_ptrs() argument
103 debug_assert((regid % 4) == 0); in fd5_emit_const_ptrs()
106 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) | in fd5_emit_const_ptrs()
510 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid)); in fd5_emit_vertex_bufs()
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Dfd5_compute.c143 A5XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) | in cs_program_emit()
144 A5XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) | in cs_program_emit()
/external/mesa3d/src/gallium/drivers/freedreno/ir3/
Dir3_const.h43 const struct ir3_shader_variant *v, uint32_t regid,
47 const struct ir3_shader_variant *v, uint32_t regid,
52 const struct ir3_shader_variant *v, uint32_t regid, in emit_const_prsc() argument
57 emit_const_bo(ring, v, regid, offset, size, rsc->bo); in emit_const_prsc()
67 uint32_t regid, uint32_t sizedwords) in emit_const_asserts() argument
69 assert((regid % 4) == 0); in emit_const_asserts()
71 assert(regid + sizedwords <= v->constlen * 4); in emit_const_asserts()
500 ir3_find_sysval_regid(v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) != regid(63, 0); in ir3_emit_vs_driver_params()
/external/mesa3d/src/freedreno/vulkan/
Dtu_pipeline.c493 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) | in tu6_emit_cs_config()
494 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) | in tu6_emit_cs_config()
513 regid(63, 0); in tu6_emit_vs_system_values()
516 regid(63, 0); in tu6_emit_vs_system_values()
519 regid(63, 0); in tu6_emit_vs_system_values()
522 regid(63, 0); in tu6_emit_vs_system_values()
525 regid(63, 0); in tu6_emit_vs_system_values()
528 regid(63, 0); in tu6_emit_vs_system_values()
531 regid(63, 0); in tu6_emit_vs_system_values()
585 if (l->var[idx].regid == v->outputs[k].regid) in tu6_link_streamout()
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Dtu_clear_blit.c365 .regid = regid(0, 3), in r3d_common()
371 .regid = regid(0, 0), in r3d_common()
375 .regid = regid(1, 0), in r3d_common()
382 vs.outputs[1].regid = regid(1, 1); in r3d_common()
402 .regid = regid(0, 0), in r3d_common()
/external/mesa3d/src/freedreno/computerator/
Da6xx.c162 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) | in cs_program_emit()
163 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) | in cs_program_emit()
186 emit_const(struct fd_ringbuffer *ring, uint32_t regid, in emit_const() argument
191 debug_assert((regid % 4) == 0); in emit_const()
196 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) | in emit_const()
/external/mesa3d/src/freedreno/decode/
Dpgmdump2.c266 uint32_t regid; member
275 R(c, regid, 'c'); in decode_shader_constant_block()
/external/mesa3d/src/gallium/drivers/r600/sb/
Dsb_valtable.cpp367 value* sb_value_pool::create(value_kind k, sel_chan regid, in create() argument
370 value *v = new (np) value(size(), k, regid, ver); in create()
Dsb_shader.cpp246 value* shader::create_value(value_kind k, sel_chan regid, unsigned ver) { in create_value() argument
247 value *v = val_pool.create(k, regid, ver); in create_value()

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